• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.182-189
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• 2011

In this work, a tunneling field-effect transistor (TFET) based on heterojunctions of compound and Group IV semiconductors is introduced and simulated. TFETs based on either silicon or compound semiconductors have been intensively researched due to their merits of robustness against short channel effects (SCEs) and excellent subthreshold swing (SS) characteristics. However, silicon TFETs have the drawback of low on-current and compound ones are difficult to integrate with silicon CMOS circuits. In order to combine the high tunneling efficiency of narrow bandgap material TFETs and the high mobility of III-V TFETs, a Type-I heterojunction tunneling field-effect transistor (I-HTFET) adopting $Ge-Al_xGa_{1-x}As-Ge$ system has been optimized by simulation in terms of aluminum (Al) composition. To maximize device performance, we considered a nanowire structure, and it was shown that high performance (HP) logic technology can be achieved by the proposed device. The optimum Al composition turned out to be around 20% (x=0.2).

• ETRI Journal
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• v.41 no.6
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• pp.829-837
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• 2019

The p-type nanowire field-effect transistor (FET) with a SiGe shell channel on a Si core is optimally designed and characterized using in-depth technology computer-aided design (TCAD) with quantum models for sub-10-nm advanced logic technology. SiGe is adopted as the material for the ultrathin shell channel owing to its two primary merits of high hole mobility and strong Si compatibility. The SiGe shell can effectively confine the hole because of the large valence-band offset (VBO) between the Si core and the SiGe channel arranged in the radial direction. The proposed device is optimized in terms of the Ge shell channel thickness, Ge fraction in the SiGe channel, and the channel length (L_g) by examining a set of primary DC and AC parameters. The cutoff frequency (f_T) and maximum oscillation frequency (f_max) of the proposed device were determined to be 440.0 and 753.9 GHz when L_g is 5 nm, respectively, with an intrinsic delay time (τ) of 3.14 ps. The proposed SiGe-shell channel p-type nanowire FET has demonstrated a strong potential for low-power and high-speed applications in 10-nm-and-beyond complementary metal-oxide-semiconductor (CMOS) technology.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.6 no.2
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• pp.95-99
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• 2006

A tape feeder of a SMD(Surface Mount Device) mounter is a device that sequentially feeds electronic components on a tape reel to the pick-up system of the mounter. As components are getting much smaller, feeding accuracy of a feeder becomes one of the most important factors for successful component pick-up. Therefore, it is critical to keep the feeding accuracy to a specified level in the assembly and production of tape feeders. This paper describes a tape feeder inspection system that was developed to automatically measure and to inspect feeding accuracy using machine vision. It consists of a feeder base, an image acquisition system, and a personal computer. The image acquisition system is composed of CCD cameras with lens, LED illumination systems, and a frame grabber inside the PC. This system loads up to six feeders at a time and inspects them automatically and sequentially. The inspection software was implemented using Visual C++ on Windows with easily usable GUI. Using this system, we can automatically measure and inspect the quality of ail feeders in production process by analyzing the measurement results statistically.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.3 no.2
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• pp.161-165
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• 2003

In this paper, we investigate the issues on the design and implementation of tele-operation system based on the haptic interface. Here, the 3-DOF haptic device and the X-Y-Z stage are employed as master controller and slave system respectively. For this master-slave system, the force feedback algorithm, the modeling of virtual environments and the control method of X-Y-Z stage are presented. In this paper, internet network is used for data communication between master and slave. We construct virtual environment of the real convex surface from the force-feedback in controlling the X-Y-Z stage and measuring the force applied by the 3-DOF haptic device.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.212-215
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• 2005

The needs of larger screen in mobile device would be increased as the time of ubiquitous and convergence is coming. And, the type of mobile device has been evolved from bar, slide to row. Recently, the study on the multi-display screen which has seamless gap between two display panel has been published, and moreover the System On Chip(SOC) design strategy of core chip has been the most promising Field-Programmable Gate Array(FPGA) technology in the display system. Therefore, in this paper, we proposed the design technique of SOC and evaluated the effectiveness with Very high speed Hardware Description Language(VHDL) Intellectual Property (IP) for the operation of multi display device driver. Also, This IP design would be to allow any kind of user interface in control system.

• Fire Science and Engineering
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• v.10 no.2
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• pp.28-39
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• 1996

A recently developed electro-thermal simulation methodology is used to analyze the behavior of a PWM(Pulse-Width-Modulated) voltage source inverter which uses IGBT(Insulated Gate Bipolar Transistor) as the switching devices. In the electro-thermal network simulation methdology, the simulator solves for the temperature distribution within the power semiconductor devices(IGBT electro-thermal model), control logic circuitry, the IGBT gate drivers, the thermal network component models for the power silicon chips, package, and heat sinks as well as the current and voltage within the electrical network. The thermal network describes the flow of heat form the chip surface through the package and heat sink and thus determines the evolution of the chip surface temperature used by the power semiconductor device models. The thermal component model for the device silicon chip, packages, and heat sink are developed by discretizing the nonlinear heat diffusion equation and are represented in component from so that the thermal component models for various package and heat sink can be readily connected to on another to form the thermal network.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.4
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• pp.1850-1858
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• 2014

The object of this study is to develop an cooling control algorithm for electronics devices of the electric vehicle. In order to estimate the existing cooling control logic of the electronic devices for the small and medium sized electric vehicle, the experiments on the coolant temperature variation of the cooling system were conducted under 4 different seasons conditions. As a result, the existing cooling control logic were overcooled when it was compared with the reference temperature for a required cooling load. In addition, the newly developed optimum cooling control logic for improving the mileages of the tested electric vehicle with consideration of the ambient temperature, vehicle speed, and refrigerant temperature of the air conditioning on/off is necessary.

• Proceedings of the KSR Conference
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• 2007.11a
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• pp.623-628
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• 2007

Metro Subway System is widely known as the leader of public transportation in a metropolitan area. The signal interlocking is one of the most important organs that plays a major role in the system. By improving the quality of signal interlocking on of the traffic system and keeping its maintenance on a high level will not only repair the current state, but it will also let the PLC(Programmable Logic Controller). The Non-Vital relay of No. 3, 4 Line are the most one of the unstable system, device, which underwent a process of fine manufacture establishment and a close examination, obtained as a new device. Utilizing the equipment with cautious preservation on the system will enhance the current state of the signal device. Especially, the test for improvement and development based upon the technique that decreases the frequency of defect produced will further precipitate its efficiency. With authorization of imposing the newly made equipment will bring improvement to the signal technology and to the industry at largest extent.

• Korean Journal of Optics and Photonics
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• v.18 no.1
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• pp.50-55
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• 2007

Using the Selective Area Growth (SAG) technology of Metal Organic Chemical Vapor Deposition (MOCVD), we successfully integrated an active device and passive devices on the same substrate. In other words, we integrated a Semiconductor Optical Amplifier (SOA) as an active device and an S-bend waveguide and a Multi Mode Interference (MMI) waveguide as passive devices. The SOA is successfully integrated with passive devices on the same substrate. The Cross-Gain Modulation (XGM) characteristic of the integrated SOA and the loss of an MMI and an S-bend waveguide were measured. Measured XGM characteristics of the SOA showed an extinction ratio of 8.82 dB. The total loss of the MMI and S-bend waveguide was 18 dB.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.8-22
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• 2014

In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (VTH) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted silicon-on-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmented-channel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.