• Journal of applied mathematics & informatics
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• 제28권5_6호
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• pp.1477-1487
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• 2010

In this paper, we give a solving approach based on a logarithmic-exponential multiplier penalty function for the constrained minimization problem. It is proved exact in the sense that the local optimizers of a nonlinear problem are precisely the local optimizers of the logarithmic-exponential multiplier penalty problem.

• 대한수학회보
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• 제47권3호
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• pp.527-540
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• 2010

We characterize the boundedness and compactness of the weighted composition operator on the logarithmic Bloch space $\mathcal{L}\ss=\{f{\in}H(D):sup_D(1-|z|^2)ln(\frac{2}{1-|z|})|f'(z)|$<+$\infty$ and the little logarithmic Bloch space ${\mathcal{L}\ss_0$. The results generalize the known corresponding results on the composition operator and the pointwise multiplier on the logarithmic Bloch space ${\mathcal{L}\ss$ and the little logarithmic Bloch space ${\mathcal{L}\ss_0$.

• 대한임베디드공학회논문지
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• 제15권5호
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• pp.235-242
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• 2020

This paper analyzes the effect of reduced output width of the truncated logarithmic multiplication and application to inferences using convolutional neural networks (CNNs). For small hardware overhead, output width is reduced in the truncated Mitchell multiplier, so that fractional bits in multiplication output are minimized in error-resilient applications. This analysis shows that when reducing output width in the truncated Mitchell multiplier, even though worst-case relative error increases, average relative error can be kept small. When adopting 8 fractional bits in multiplication output in the evaluations, there is no significant performance degradation in target CNNs compared to existing exact and original Mitchell multipliers.

• ETRI Journal
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• 제43권4호
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• pp.684-693
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• 2021

This paper presents a low-cost two-stage approximate multiplier for bfloat16 (brain floating-point) data processing. For cost-efficient approximate multiplication, the first stage implements Mitchell's algorithm that performs the approximate multiplication using only two adders. The second stage adopts the exact multiplication to compensate for the error from the first stage by multiplying error terms and adding its truncated result to the final output. In our design, the low-cost multiplications in both stages can reduce hardware costs significantly and provide low relative errors by compensating for the error from the first stage. We apply our approximate multiplier to the convolutional neural network (CNN) inferences, which shows small accuracy drops with well-known pre-trained models for the ImageNet database. Therefore, our design allows low-cost CNN inference systems with high test accuracy.

• Journal of Electrical Engineering and Technology
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• 제3권3호
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• pp.430-435
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• 2008

In the paper, an algorithm called a Constraint algorithm is proposed to solve the fan-in problem occurred in ADC encoding circuits. The Flash ADC architecture uses a double-base number system (DBNS). The DBNS has known to represent the multi-dimensional logarithmic number system (MDLNS) used for implementing the multiplier accumulator architecture of FIR filter in digital signal processing (DSP) applications. The authors use the DBNS with the base 2 and 3 to represent binary output of ADC. A symmetric map is analyzed first, and then asymmetric map is followed to provide addition read DBNS to DSP circuitry. The simulation results are shown for the Double-Base Integer Encoder (DBIE) of the 6-bit ADC to demonstrate an effectiveness of the Constraint algorithm, using $0.18{\mu}\;m$ CMOS technology. The DBIE’s processing speed of the ADC is fast compared to the FAT tree encoder circuit by 0.95 GHz.

• 설비공학논문집
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• 제10권6호
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• pp.732-742
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• 1998

Prediction method for heat transfer coefficients in a horizontal smooth tube with forced convection condensation is proposed. In this paper, the analogy between momentum and heat transfer was applied to an annular flow regime and the logarithmic velocity distribution is applied to describe the velocity profile within the liquid film. Prediction results are compared with those of experimental ones. The test refrigerants are R113, R22, R134a, R407C(R33/R125/R134a, 23/25/52 wt%), R410A(R32/R125, 50/50 wt%) and R134a＋R123(R134a/R123, 85.5/14.5 wt%) which are used under operating conditions in a condenser of air-conditioner. The proposed prediction method shows good agreement with experimental data within$\pm 30%$ for pure refrigerants. For the mixture refrigerants including the ternary mixture refrigerant R407C, condensation heat transfer from this study are higher than those from experiments. By correcting the constant in two-phase frictional multiplier, the predicated heat transfer coefficients become similar to the experimental results.

• 융합신호처리학회논문지
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• 제9권3호
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• pp.224-229
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• 2008

In the paper, a new Constraint algorithm is proposed to solve the fan-in problem occurred in the encoding circuitry of an ADC. The Flash ADC architecture uses a Double-Base Number System(DBNS). The DBNS has been known to represent the Multidimensional Logarithmic Number System (MDLNS) used for implementing the multiplier accumulator architecture of FIR filter in Digital Signal Processing (DSP) applications. The authors use the DBNS with the base 2 and 3 in designing ADC encoder circuits, which is called as Double Base Integer Encoder(DBIE). A symmetric map is analyzed first, and then asymmetric map is followed to provide addition ready DBNS for DSP circuitry. The simulation results of the DBIE circuits in 6-bit and 8-bit ADC show the effectiveness of the Constraint algorithm with $0.18{\mu}m$ CMOS technology. The DBIE yields faster processing speed compared to the speed of Fat Tree Encoder (FAT) circuits by 17% at more power consumption by 39%.