• Journal of The Korean Astronomical Society
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• v.29 no.spc1
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• pp.341-342
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• 1996

We present here the solar LOG GF values obtained using the Liege solar at las and the standard solar photospheric models for the spectral lines in the wavelength range ${\lambda}{\lambda}$ 6209 - 6273 ${\AA}$. These log gf values shall be used to interpret a high resolution spectra of the star $\gamma$ Draconics.

• Journal of The Korean Astronomical Society
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• v.29 no.spc1
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• pp.343-344
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• 1996

Solar IR spectra have been utilised by us to derive log gf values for atomic lines due to 17 chemical elements. in the J and H bands, i.e. in the wavelength ranges 1.00 - 1.34 ${\mu}m$ and 1.49 - 1.80 ${\mu}m$ respectively. The observed central line depths were based on the FTS atlases published at. Liege and KPNO. We also reprot new log gf values for 51 lines for which neither theoretical nor experimental values are available till date.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.701-703
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• 2000

본 논문에서는 정규 기저 표현(normal bases repersentation)을 갖는 GF(2n)상에서의 병렬 멱승 연산에 있어서 2 가지의 개선 사항을 기술한다. 첫째는,k를 윈도우 길이로 할 때 라운드가 [log k]+[log[n/k]]로 고정된 경우에 현재까지 알려진 방법보다 더 작은 수의 프로세서를 갖는 방안이다. 둘째는 점근적인(asymptotic)분석을 통하여 GF(2n)상에서의 병렬 멱승 연산이 O(n/log2n)개의 프로세서로 O(logn)라운드에 수행될 수 있음을 보인다. 이것은 m로세서 $\times$라운드의 바운드를 O(n/logn)으로 하는 것으로 이전까지 알려졌던 O(n)을 개선한 것이다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.23-30
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• 2008

Recently, a considerable number of studies have been conducted on pairing based cryptosystems. The efficiency of pairing based cryptosystems depends on finite fields, similar to existing public key cryptosystems. In general, pairing based ctyptosystems are defined over finite fields of chracteristic three, GF($3^m$), based on trinomials. A multiplication in GF($3^m$) is the most dominant operation. This paper proposes a new most significant digit(MSD)-first digit- serial multiplier. The proposed MSD-first digit-serial multiplier has the same area complexity compared to previous multipliers, since the modular reduction step is performed in parallel. And the critical path delay is reduced from 1MUL+(log ${\lceil}n{\rceil}$+1)ADD to 1MUL+(log ${\lceil}n+1{\rceil}$)ADD. Therefore, when the digit size is not $2^k$, the time delay is reduced by one addition.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.8
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• pp.453-464
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• 2004

In order to solve the well-known drawback of reduced flexibility that is associate with ASIC implementations, this paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for field programmable gate arrays (FPGAs) implementations of elliptic curve cryptographic processor. The proposed arithmetic unit is based on the binary extended GCD algorithm and the MSB-first multiplication scheme, and designed as systolic architecture to remove global signals broadcasting. The proposed architecture can perform both division and multiplication in GF(2$^{m}$ ). In other word, when input data come in continuously, it produces division results at a rate of one per m clock cycles after an initial delay of 5m-2 in division mode and multiplication results at a rate of one per m clock cycles after an initial delay of 3m in multiplication mode respectively. Analysis shows that while previously proposed dividers have area complexity of Ο(m$^2$) or Ο(mㆍ(log$_2$$^{m}$ )), the Proposed architecture has area complexity of Ο(m), In addition, the proposed architecture has significantly less computational delay time compared with the divider which has area complexity of Ο(mㆍ(log$_2$$^{m}$ )). FPGA implementation results of the proposed arithmetic unit, in which Altera's EP2A70F1508C-7 was used as the target device, show that it ran at maximum 121MHz and utilized 52% of the chip area in GF(2$^{571}$ ). Therefore, when elliptic curve cryptographic processor is implemented on FPGAs, the proposed arithmetic unit is well suited for both division and multiplication circuit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.9
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• pp.1538-1544
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• 2006

This paper proposes a non-systolic parallel $AB^2+C$ Computing unit based on irreducible AOP order m of $GF(2^m)$. Proposed circuit have only AND gates and EX-OR gates, composes of cyclic shift operation, multiplication operation power operation power-sum operation and addition operation using a merry irreducible AOP. Suggested operating a method have an advantage high speed data processing, low power and integration because of only needs AND gates and EX-OR gates. $AB^2+C$ computing unit has delay-time of $T_A+(1+[log^m_2])T_X$.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2002.11a
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• pp.84-87
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• 2002

최근 정보보호의 중요성이 커짐에 따라 암호이론에 대한 관심이 증가되고 있다. 이 중 Galois 체 GF(2$^{m}$ )은 대부분의 암호시스템에서 사용되며, 특히 공개키 기반 암호시스템에서 주로 사용된다. 이들 암호시스템에서는 GF(2$^{m}$ )에서 정의된 연산, 즉 덧셈, 뺄셈, 곱셈 및 곱셈 역원 연산을 기반으로 구축되므로, 이들 연산을 고속으로 계산하는 것이 중요하다. 이들 연산 중에서 곱셈 역원이 가장 time-consuming하다. Fermat의 정리를 기반으로 하고, GF(2$^{m}$ )에서 정규기저를 사용해서 곱셈 역원을 고속으로 계산하기 위해서는 곱셈 횟수를 감소시키는 것이 가장 중요하며, 이와 관련된 방법들이 많이 제안되어 왔다. 이 중 Itoh와 Tsujii가 제안한 방법[2]은 곱셈 횟수를 O(log m)까지 감소시켰다. 본 논문에서는 Itoh와 Tsujii가 제안한 방법을 이용해서, m=2$^n$인 경우에 곱셈 역원을 고속으로 계산하는 방법을 제안한다. 본 논문의 방법은 필요한 곱셈 횟수가 Itoh와 Tsujii가 제안한 방법 보다 적으며, m-1의 분해가 기존의 방법보다 간단하다.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.771-774
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• 1998

In this paper proposes a new bit-parallel structure for a multiplier over GF((Pn)m), with k-nm. Mastrovito Multiplier, Karatsuba-ofman algorithm are applied to the multiplication of polynomials over GF(2n). This operation has a complexity of order O(k log p3) under certain constrains regardig k. A complete set of primitive field polynomials for composite fields is provided which perform modulo reduction with low complexity. As a result, multiplier for fields GF(Pk) with low gate counts and low delays are constructed. The architectures are highly modular and thus well suited for VLSI implementation.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.5
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• pp.29-36
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• 2004

This study focuses on the arithmetical methodology and hardware implementation of low-system-complexity multiplier over GF(2$^{m}$ ) using the trinomial of degree a The proposed parallel-in parallel-out operator is composed of MR, PP, and MS modules, each can be established using the regular array structure of AND and XOR gates. The proposed multiplier is composed of $m^2$ 2-input AND gates and $m^2$-1 2-input XOR gates, and the propagation delay is $T_{A}$+(1+[lo $g_2$$^{m}$ ]) $T_{x}$ . Comparison result of the related multipliers of GF(2$^{m}$ ) are shown by table, it reveals that our operator involve more regular and generalized then the others, and therefore well-suited for VLSI implementation. Moreover, our multiplier is more suitable for any other GF(2$^{m}$ ) operational applications.s.

• Journal of the Korea Society of Computer and Information
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• v.17 no.3
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• pp.1-10
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• 2012

A low-complexity Multiplication over GF(2m) and multiplier circuit has been proposed by using cyclic-shift coefficients and the irreducible trinomial. The proposed circuit has the parallel input/output architecture and shows the lower-complexity than others with the characteristics of the cyclic-shift coefficients and the irreducible trinomial modular computation. The proposed multiplier is composed of $2m^2$ 2-input AND gates and m (m+2) 2-input XOR gates without the memories and switches. And the minimum propagation delay is $T_A+(2+{\lceil}log_2m{\rceil})T_X$. The Proposed circuit architecture is well suited to VLSI implementation because it is simple, regular and modular.