• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.2
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• pp.258-264
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• 2011

In this paper, we designed a frequency synthesizer with a low phase noise and fast lock time and excellent spurious characteristics using the offset-PLL(Phase Locked Loop) that is used in GSM(Global System for Mobile communications). The proposed frequency synthesizer has low phase noise using three times down conversion and third offset frequency of this synthesizer is created by DDS(Direct Digital Synthesizer) to have high frequency resolution. Also, this synthesizer has fast switching speed using DAC(Digital to Analog Converter). but phase noise degraded due to DAC. we improved performance using the DAC noise filter.

• Journal of Ocean Engineering and Technology
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• v.26 no.5
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• pp.25-30
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• 2012

This study examined the use of LIT (lock-in infrared thermography) to detect defects in the welded parts of ships and offshore structures. A quantitative analysis was used with the filtering and texture measurement of image processing techniques to find the optimized experimental condition. We verified the reliability of our methods by applying image processing techniques in order to normalize the evaluations of comparative images that showed a phase difference. In addition, it was found that a low to mid-range intensity of light exposure on the surface showed good results, whereas high exposure did not provide significant results. A lock-in frequency of around 0.1 Hz was satisfactory regardless of the intensity of the light source. In addition, making the integration time of the thermography camera inversely proportional to the intensity of the exposed light source during the experiment provided good results.

• Journal of Ocean Engineering and Technology
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• v.7 no.1
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• pp.114-123
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• 1993

In is well known that a cyclic Karman vortex street is thrown out periodically from cylinder whose axis is vertical to the bulk flow. When the cylinder is vibrating in the frequency close to that of Karman vortex street, the vortex shedding frequency is locked onto that of cylinder. While there are many experimental studies for this phenomenon compared with analytical studies by numerical calculation, are very limited. In this study, a new algorithm for moving boundary is proposed and a simulator is develoed, which can deal with this phenomenon with experimental studies.

• Korean Journal of Optics and Photonics
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• v.11 no.5
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• pp.330-334
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• 2000

A new pha~e lock loop (PLL) IS proposed and demonstrated fat clock recovery from 40 Gblt/s time-dIvision-multiplexed (TDM) optical pulse tri.lin, The proposed clock lecovery scheme lmproves the Jitter effecl cOlmng from the clock. pulse laser of harmonically-mode locked flber laser The cross-corrdation frequency component between the optical Signa] and an optical clock pulse tram is deteCled as a fonr-wave-mixing (FWM) SIgnal generated in SOA. The lock-in freqnency range of the clod. recovery IS found to be within 10 KHz. 0 KHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.152-156
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• 2013

This paper presents a fast-lock dual-loop successive approximation register-controlled duty-cycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast duty-cycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than ${\pm}0.86%$ for a wide input duty-cycle range of 15-85 % over a wide frequency range of 0.5-2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-${\mu}m$, 1.8-V CMOS process and occupies an active area of $0.075mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.65-70
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• 2008

A novel fast locking dual-loop integer-N phase locked loop(PLL) with adaptive bandwidth scheme is presented. When the PLL is out-of-lock, bandwidth becomes much wider than 1/10 of channel spacing with the wide bandwidth loop. When the PLL is near in-lock, bandwidth becomes narrower than 1/10 of channel spacing with the narrow bandwidth loop. The proposed PLL is designed based on a $0.35{\mu}m$ CMOS process with a 3.3V supply voltage. Simulation results show the fast look time of $50{\mu}s$ for an 80MHz frequency jump in a 200KHz channel spacing PLL with almost 14 times wider bandwidth than the channel spacing.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.12
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• pp.28-34
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• 2011

In this paper, a PLL frequency synthesizer for RSSI applications is designed by phase noise analysis. Required synthesizer performance is achieved by optimizing the noise performance of PLL components and a loop transfer function, since its phase noise, lock time, and spur suppression capability are determined by the performance of loop components and loop filter characteristics. As an application example, a PLL frequency synthesizer for RSSI applications, which operates at the frequency of 2.288GHz, is designed using the phase noise analysis. The validity of the design technique is proved by experiments.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.22 no.1
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• pp.107-111
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• 2013

The gyroscopes have been used as a suitable inertial instrument for the navigation guidance and attitude controls. The accuracy as very sensitive sensor is limited by the lock-in region (dead band) due to the frequency coupling between two counter-propagating waves at low rotation rates. This frequency coupling gives no phase difference, and an angular increment is not detected. This problem can be overcome by mechanically dithering the gyroscope. This paper presents the design method of mechanical dither by the theoretical considerations and the verification of the theoretical equations through FEM applications. As a result, comparing to the past result, the maximum prediction error of resonant frequency was within 3 percent and peak dither rate was within 5 percent. It was found that the theoretical equations can be feasible for the mechanical performance of dither.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.6
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• pp.1949-1954
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• 2010

The gyroscopes have been used as a suitable inertial instrument for the navigation guidance and attitude controls. The accuracy as very sensitive sensor is limited by the lock-in region(dead band) due to the frequency coupling between two counter-propagating waves at low rotation rates. This frequency coupling gives no phase difference, and an angular increment is not detected. This problem can be overcome by mechanically dithering the gyroscope. This paper presents the design method of mechanical dither by the theoretical considerations and the verification of the theoretical equations through FEM(Finite Element Method) applications. As a result, the maximum prediction error of resonant frequency and peak dither rate was under 5 percent. The theoretical equations for the mechanical performances of dither can be said to be feasible.

• Transactions of the Korean Society of Automotive Engineers
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• v.17 no.3
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• pp.74-80
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• 2009

The objective of this paper was to investigate the slip rate and the slip frequency number of damper clutch of torque converter in 2.4L passenger vehicle with 5-speed A/T and analyze the effect of slip control and control strategy on driving characteristics and the fuel economy. The newly developed torque converter with the more durable wet friction material and the slip-controlled damper clutch system, the DCC system, was installed, which was easily compatible and amendable of the lock-up clutch of the base system. The vehicle has been tested on the fuel economy modes such as FTP-75, HWFET and NEDC (ECE15+EUDC) driving cycle at chassis dynamometer. The DCC mode (II), of which the control strategy had both the lock-up and the slip-controlled clutch, and the DCC mode (I) with full slip-controlled clutch were compared with the base system with only the lock-up clutch. As the research result, comparison to base system, the fuel consumption of the vehicle with the DCC control (II) was effectively improved by 6.6% and 7.7% on FTP-75 and NEDC mode.