• 한국컴퓨터산업학회논문지
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• 제6권5호
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• pp.757-766
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• 2005

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6T Full CMOS SRAM had been continued as the technology advances, However, conventional 6T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6T Full CMOS SRAM is $70{\sim}90F^{2}$, which is too large compared to $8{\sim}9F^{2}$ of DRAM cell. With 80nm design rule using 193nm ArF lithography, the maximum density is 72M bits at the most. Therefore, pseudo SRAM or 1T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed $S^{3}$ cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^{3}$ SRAM cell technology with 100nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• 한국전기전자재료학회논문지
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• 제19권4호
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• pp.314-321
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• 2006

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6 T Full CMOS SRAM had been continued as the technology advances. However, conventional 6 T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6 T Full CMOS SRAM is $70{\sim}90\;F^2$, which is too large compared to $8{\sim}9\;F^2$ of DRAM cell. With 80 nm design rule using 193 nm ArF lithography, the maximum density is 72 Mbits at the most. Therefore, pseudo SRAM or 1 T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64 M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6 T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S3 cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^3$ SRAM cell technology with 100 nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1996년도 Proceedings of the Korea Automatic Control Conference, 11th (KACC); Pohang, Korea; 24-26 Oct. 1996
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• pp.207-210
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• 1996

This paper describes the analysis of the operation of the switched snubber in order to depress the surge voltage in the MOS-FET inverter. In this paper, the N-channel MOS-FET which operates faster than the P-channel MOS-FET was used for the inverter circuit. So, the inverter and switched snubber can operate at high-frequency in the order of MHz. The cause of generating the surge voltage in the high frequency inverter has been cleared, and then how to depress the surge voltage using the switched snubber consisting of an N-channel MOS-FET has been given. Furthermore, described is the power loss within the switched snubber which is made of an N-channel MOS-FET. The inverter having the N-channel MOS-FET used as a switched snubber can drive such a low impedance load such as mega-sonic transducer for a mega-sonic studied cleaner sufficiently.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.970-973
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• 2003

Abstract An idea to redce the direct-path short circuit current of the CMOS digital integrated circuit is present. The sample circuit model of the CMOS digital circuit is the CMOS current-control digital output driver circuit, which are also suitable for the low voltage supply integrated circuits as the simple digital inverter, are present in this title. The circuit consists of active MOS load as the current control source, which construct from the saturated n-channel and p-channel MOSFET and the general CMOS inverter circuits. The saturated MOSFET bias can control the output current and the frequency response of the circuit. The experimental results show that lower short circuit current control can make the lower frequency response of the circuit.

• 전자공학회논문지SC
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• 제48권2호
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• pp.15-21
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• 2011

본 논문에서는 $0.35{\mu}m$ CMOS 공정을 이용하여 태양 에너지 하베스팅을 위한 에너지 관리 시스템을 설계하였다. 태양 에너지 관리 시스템은 ISC(Integrated Solar Cell), voltage booster, MPPT(Maximum Power Point Tracker) control unit으로 구성된다. ISC의 개방전압은 약 0.5V이고, 단락 전류는 약 $15{\mu}A$이다. Voltage booster는 뒷단에 약 1.5V로 승압된 전압을 공급한다. MPPT control unit은 ISC가 MPP점에 도달 하였을 때, load로 전력이 전달될 수 있도록 pMOS 스위치를 동작시킨다. SEMU(Solar Energy Management Unit)의 크기는 패드를 포함하여 $360{\mu}m{\times}490{\mu}m$이다. ISC의 면적은 $500{\mu}m{\times}2000{\mu}m$이다. 제작된 칩을 측정한 결과 설계된 SEMU가 ISC에서 수확된 에너지에 대해 MPPT control 동작을 제대로 수행하는 것을 확인하였다. 측정된 MPP 전압범위는 약 370mV∼420mV이다.

• 대한전자공학회논문지SD
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• 제47권4호
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• pp.62-68
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• 2010

본 논문에서는 주로 소면적 구현을 위하여 세그먼트 부분 정합 기법을 적용한 10비트 100MS/s DAC를 제안한다. 제안하는 DAC는 비교적 적은 수의 소자로도 요구되는 선형성을 유지하면서 고속으로 부하저항의 구동이 가능한 세그먼트 전류 구동방식 구조를 사용하였으며, 제안하는 세그먼트 부분 정합 기법을 적용하여 정합이 필요한 전류 셀들의 숫자와 크기를 줄였다. 또한, 전류 셀에는 작은 크기의 소자를 사용하면서도 높은 출력 임피던스를 얻을 수 있도록 이중-캐스코드 구조를 채용하였다. 시제품 DAC는 0.13um CMOS 공정으로 제작되었으며, 유효 면적의 크기는 $0.13mm^2$이다. 시제품 측정 결과, 3.3V의 전원전압과 $1V_{p-p}$의 단일 출력 범위 조건에서 $50{\Omega}$의 부하저항을 구동할 때 DNL 및 INL은 각각 -0.73LSB, -0.76LSB 수준이며, SFDR은 100MS/s의 동작 속도에서 최대 58.6dB이다.