• Journal of IKEEE
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• v.13 no.2
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• pp.126-131
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• 2009

To overcome short channel effects, wrap-around field effect transistors have drawn a great deal of attention for their superior electrostatic coupling between the channel and the surrounding gate electrode. In this paper, we introduce a bottom-up technique to fabricate a wrap-around field effect transistor using silicon nanowires as the conduction channel. Device fabrication was consisted mainly of electron-beam lithography, dielectrophoresis to accurately align the nanowires, and the formation of gate electrode using electrochemical deposition. The electrolyte for electrochemical deposition was made up of non-toxic organic-based solution and liquid nitrogen was used as a method of maintaining the shape of polymethyl methacrylate(PMMA) during the process of electrochemical deposition. Patterned PMMA can be used as a nano-template to produce wrap-around gate nano-structures.

• 한국생물공학회:학술대회논문집
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• 2005.04a
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• pp.88-92
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• 2005

Aptamer is the single-stranded oligonucleotide which binds to various target molecules such as proteins, peptides, lipids and small organic molecules with high affinity and specificity. DNA aptamers specific for the $17{\beta}-estradiol$ were selected by SELEX (Systematic Evolution of Ligands by EXponential enrichment) process from a random DNA library. These DNA aptamers have a high affinity to $17{\beta}-estradiol$ as an endocrine disrupting chemical. Nanowell and $200{\mu}m$ gold electrode were used as substrate for DNA aptamer immobilization and electrochemical analysis. Especially, nanowell gold electrode was fabricated by e-beam lithography. The size of single nanowell is 130nm and 40,000 nanowells were deposited on one gold electrode. The immobilization method was based on the interaction between the biotinylated aptamer and streptavidin deposited on gold electrode previously. Immobilization procedure was optimized by surface plasma resonance (SPR) and electrochemical analysis. After the immobilization of DNA aptamer on streptavidin modified gold electrode, $17{\beta}-estradiol$ solution was treated on aptamer immobilized gold electrode. The current of gold electrode was decreased by the binding of $17{\beta}-estradiol$ to DNA aptamer immobilized on gold electrode. However, in negative control experiments of 1-aminoanthraquinone and 2-methoxynaphthalene, the current was rarely decreased. And more sensitive data was obtained from nanowell gold electrode comparing with $200{\mu}m$ gold electrode.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2016.11a
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• pp.128-128
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• 2016

Cu 배선폭 미세화 기술은 반도체 디바이스의 성능 향상을 위한 핵심 기술이다. 현재 배선 기술은 lithography, deposition, planarization등 종합적인 공정 기술의 발전에 따라 10x nm scale까지 감소하였다. 하지만 지속적인 feature size 감소를 위하여 요구되는 높은 공정 기술 및 비용과 배선폭 미세화로 인한 재료의 물리적 한계로 인하여 배선폭 미세화를 통한 성능의 향상에는 한계가 있다. 배선폭 미세화를 통한 2차원적인 집적도 향상과는 별개로 chip들의 3차원 적층을 통하여 반도체 디바이스의 성능 향상이 가능하다. 칩들의 3차원 적층을 위해서는 별도의 3차원 배선 기술이 요구되는데, TSV(through-Si-via)방식은 Si기판을 관통하는 via를 통하여 chip간의 전기신호 교환이 최단거리에서 이루어지는 가장 진보된 형태의 3차원 배선 기술이다. Si 기판에 $50{\mu}m$이상 깊이의 via 및 seed layer를 형성 한 후 습식전해증착법을 이용하여 Cu 배선이 이루어지는데, via 내부 Cu ion 공급 한계로 인하여 일반적인 공정으로는 void와 같은 defect가 형성되어 배선 신뢰성에 문제를 발생시킨다. 이를 해결하기 위해 각종 유기 첨가제가 사용되는데, suppressor를 사용하여 Si 기판 상층부와 via 측면벽의 Cu 증착을 억제하고, accelerator를 사용하여 via 바닥면의 Cu 성장속도를 증가시켜 bottom-up TSV filling을 유도하는 방식이 일반적이다. 이론적으로, Bottom-up TSV filling은 sample 전체에서 Cu 성장을 억제하는 suppressor가 via bottom의 강한 potential로 인하여 국부적 탈착되고 via bottom에서만 Cu가 증착되어 되어 이루어지므로, accelerator가 없이도 void-free TSV filling이 가능하다. Accelerator가 Suppressor를 치환하여 오히려 bottom-up TSV filling을 방해한다는 보고도 있었다. 본 연구에서는 유기 첨가제의 치환으로 인한 TSV filling performance 저하를 방지하고, 유기 첨가제 조성을 단순화하여 용액 관리가 용이하도록 하기 위하여 suppressor만을 이용한 TSV filling 연구를 진행하였다. 먼저, suppressor의 흡착, 탈착 특성을 이해하기 위한 연구가 진행되었고, 이를 바탕으로 suppressor만을 이용한 bottom-up Cu TSV filling이 진행되었다. 최종적으로 $60{\mu}m$ 깊이의 TSV를 1000초 내에 void-free filling하였다.

• Journal of the Korea Computer Industry Society
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• v.6 no.5
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• pp.757-766
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• 2005

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6T Full CMOS SRAM had been continued as the technology advances, However, conventional 6T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6T Full CMOS SRAM is $70{\sim}90F^{2}$, which is too large compared to $8{\sim}9F^{2}$ of DRAM cell. With 80nm design rule using 193nm ArF lithography, the maximum density is 72M bits at the most. Therefore, pseudo SRAM or 1T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed $S^{3}$ cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^{3}$ SRAM cell technology with 100nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.4
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• pp.314-321
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• 2006

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6 T Full CMOS SRAM had been continued as the technology advances. However, conventional 6 T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6 T Full CMOS SRAM is $70{\sim}90\;F^2$, which is too large compared to $8{\sim}9\;F^2$ of DRAM cell. With 80 nm design rule using 193 nm ArF lithography, the maximum density is 72 Mbits at the most. Therefore, pseudo SRAM or 1 T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64 M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6 T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S3 cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^3$ SRAM cell technology with 100 nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• Journal of the Korean Vacuum Society
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• v.15 no.4
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• pp.354-359
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• 2006

Recently, the interest in lithography without photo exposure has been increased compare to the conventional photolithography in nano meter and micrometer size patterning area. We studied a self aligned dipping of Ag solution through micro contact printing (${\mu}-CP$) with octadecyltrichlorosilane (OTS) treated polydimethylsiloxane (PDMS) soft mold. The OTS monolayer on the patterned PDMS was formed by dipping it into OTS solution. We transferred the OTS monolayer from PDMS mold to the glass. The OTS monolayer changed the surface energy from hydrophilic surface to hydrophobic surface, And then we made self aligned Ag solution patterns just after dipping the substrate, using adhesion difference of Ag solution between OTS treated hydrophobic area and non-OTS treated hydrophilic area. We finally get the Ag patterns through only dip-coating after the ${\mu}-CP$ process. And we observed surface energies on the glass substrate through the contact angle measurements as time goes on.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.1
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• pp.63-67
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• 2015

In this study, we demonstrate the change of optical characteristic by thickness of metal deposition on nano metal grid polarizer film fabrication. Nano metal grid polarizer film consists of aluminium grid polarizer layer on PET (Polyethylene phthalate) substrate. We aim at metal grid layer formation for the large nano wire grid polarizer fabrication. we draw process conditions of the nano metal grid polarizer film fabrication to improve transmittance and extinction ratio and Nano wire grid polarizer film (NWGP) film is fabricated with 140 nm pitch, 70 nm width, and 70 nm depth of metal grid on optimum design conditions. As a result, we get high optical properties of nano wire grid polarizer which is the maximum transmittance of 80% and the extinction ratio of $10^6$ at 600 nm wavelength respectively.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.35 no.4
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• pp.385-390
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• 2011

In this study, we developed a micromixer based on the non-equilibrium electrokinetics at the junction of a microchannel and nanochannel. Two fluid streams were mixed by an electro-osmotic flow and a vortex flow created as a result of the non-equilibrium electrokinetics at the junction of the microchannel and nanochannel. Initially, the microchannel was fabricated using Polydimethylsiloxane (PDMS) by the general soft lithography process and the nanochannel was created at a specific position on the microchannel by applying a high voltage. To evaluate the mixing performance of the micromixer, fluorescent distribution was analyzed by using the fluorescent dye, Rhodamine B. About 90% mixing was achieved with this novel micromixer, and this micromixer can be used in microsystems for biochemical sample analysis.

• Applied Chemistry for Engineering
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• v.24 no.5
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• pp.562-565
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• 2013

The high purity Al foil, which has an enlarged surface area by electrochemical etching process, has been used as an anode for an aluminum electrolytic capacitor. Etch pits are randomly distributed on the surface because of the existence of surface irregularities such as impurity and random nucleation of pits. Even though a large surface area was formed on the tunnel-etched Al, its applications to various fields were limited due to non-uniform tunnel morphologies. In this work, the selective electrochemical etching of aluminum was carried out by using a patterned mask fabricated by photolithographic method. The formation of etch pits with uniform distribution has been demonstrated by the optimization of experimental conditions such as current density and etching solution temperature.

• Korean Journal of Optics and Photonics
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• v.28 no.2
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• pp.53-58
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• 2017

This paper presents the design and fabrication of a planar nano-diffraction grating for an integrated miniature spectrometer module. The proposed planar nano-diffraction grating consists of nonuniform periods, to focus the reflected beams from the grating's surface, and an asymmetrical V-shaped groove profile, to provide uniform diffraction efficiency in the wavelength range from 400 to 650 nm. Also, to fabricate the nano-diffraction grating using low-cost UV-NIL technology, we analyzed the FT-IR spectrum of a uvcurable resin and optimized the conditions for the UV curing process. Then, we precisely fabricated the polymeric nano-diffraction grating within 5 nm in dimensional accuracy. The integrated spectrometer module using the fabricated polymeric planar nano-diffraction grating provides spectral resolution of 5 nm and spectral bandwidth of 250 nm. Our integrated spectrometer module using a polymeric planar nano-diffraction grating serves as a quick and easy solution for many spectrometric applications.