• 제목/요약/키워드: leakage power suppression

검색결과 22건 처리시간 0.031초

Leakage Magnetic Field Suppression Using Dual-Transmitter Topology in EV Wireless Charging

  • Zhu, Guodong;Gao, Dawei;Lin, Shulin
    • Journal of Power Electronics
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    • 제19권3호
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    • pp.625-636
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    • 2019
  • This paper proposes an active leakage magnetic field (LMF) suppression scheme, which uses the dual-transmitter (DT) topology, for EV wireless charging systems (EVWCS). The two transmitter coils are coplanar, concentric and driven by separate inverters. The LMF components generated by the three coils cancel each other out to reduce the total field strength. This paper gives a detailed theoretical analysis on the operating principles of the proposed scheme. Finite element analysis is used to simulate the LMF distribution patterns. Experimental results show that when there is no coil misalignment, 97% of the LMF strength can be suppressed in a 1kW prototype. These results also show that the impact on efficiency is small. The trade-off between LMF suppression and efficiency is revealed, and a control strategy to balance these two objectives is presented.

High Output Power and High Fundamental Leakage Suppression Frequency Doubler MMIC for E-Band Transceiver

  • Chang, Dong-Pil;Yom, In-Bok
    • Journal of electromagnetic engineering and science
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    • 제14권4호
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    • pp.342-345
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    • 2014
  • An active frequency doubler monolithic microwave integrated circuit (MMIC) for E-band transceiver applications is presented in this letter. This MMIC has been fabricated in a commercial $0.1-{\mu}m$ GaAs pseudomorphic high electron mobility transistor (pHEMT) process on a 2-mil thick substrate wafer. The fabricated MMIC chip has been measured to have a high output power performance of over 13 dBm with a high fundamental leakage suppression of more than 38 dBc in the frequency range of 71 to 86 GHz under an input signal condition of 10 dBm. A microstrip coupled line is used at the output circuit of the doubler section to implement impedance matching and simultaneously enhance the fundamental leakage suppression. The fabricated chip is has a size of $2.5mm{\times}1.2mm$.

Suppression of Leakage Current and Distortion in Variable Capacitance Devices and their Application to AC Power Regulators

  • Katsuki, Akihiko;Oki, Takuya
    • Journal of Power Electronics
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    • 제16권1호
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    • pp.66-73
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    • 2016
  • The quantity of alternating current (AC) leakage and the value of distortion factor in capacitor currents are discussed with regard to a new power component called variable capacitance device (VCD). This component has terminals for controlling its capacitance. Nonlinear dielectric characteristics are utilized in this device to vary the capacitance. When VCD operates in an AC circuit, the AC leakage from this device through direct current (DC) control voltage source increases according to the conditions of DC control voltage and so on. To solve this problem, we propose techniques for suppressing AC leakage. Although VCD has strong nonlinear characteristics, the current through the capacitor is not distorted significantly. The relations between AC leakage and the distortion in current waveforms are investigated. An application example for an AC power regulator is also introduced to evaluate the distortion in waveforms.

70-nm 이하 급 초미세 CMOS 공정에서의 누설 전류 및 동적 전류 소비 억제 내장형 SRAM 설계 (Leakage-Suppressed SRAM with Dynamic Power Saving Scheme for Future Sub-70-nm CMOS Technology)

  • 최훈대;최현영;김동명;김대정;민경식
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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    • pp.343-346
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    • 2004
  • This paper proposes a leakage-suppressed SRAM with dynamic power saying scheme for the future leakage-dominant sub-70-nm technology. By dynamically controlling the common source-line voltage ($V_{SL}$) of sleep cells, the sub-threshold leakage through these sleep cells can be reduced to be 1/10-1/100 due to the reverse body-bias effect, dram-induced barrier lowering (DIBL) and negative $V_{GS}$ effects. Moreover, the bit-ling leakage which mar introduce a fault during the read operation can be completely eliminated in this new SRAM. The dynamic $V_{SL}$ control can also reduce the bit-line swing during the write so that the dynamic power in write can be reduced. This new SRAM was fabricated in 0.35-${\mu}m$ CMOS process and more than $30\%$ of dynamic power saying is experimentally verified in the measurement. The leakage suppression scheme is expected to be able to reduce more than $90\%$ of total SRAM power in the future leakage-dominant 70-nm process.

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능동형 커먼 모드 전압 감쇄기를 통한 유도 전동기의 고주파 누설전류 억제 (Suppression of high frequency leakage current in PWM Inverter-Fed Induction Motor Drives using Active Common Mode Voltage Damper)

  • 홍순일
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2000년도 전력전자학술대회 논문집
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    • pp.186-190
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    • 2000
  • This paper propose a "Active common-mode voltage damper circuit" that capable of a suppression of a common-mode voltage produced in the PWM VSI. The four level half-bridge PWM inverter circuit and common-mode transformer are incorporated into the "Active common-mode voltage damper" the design method of which is presented Effect of "Active common-mode voltage damper" in this paper verifies a propriety and effectiveness in 2.2[kW] induction motor drive using IGBT inverter. Experimental results show that "common-mode voltage damper" makes contributions to reducing a high frequency leakage current and common-mode voltage.leakage current and common-mode voltage.

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MTCMOS Post-Mask Performance Enhancement

  • Kim, Kyo-Sun;Won, Hyo-Sig;Jeong, Kwang-Ok
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제4권4호
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    • pp.263-268
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    • 2004
  • In this paper, we motivate the post-mask performance enhancement technique combined with the Multi-Threshold Voltage CMOS (MTCMOS) leakage current suppression technology, and integrate the new design issues related to the MTCMOS technology into the ASIC design methodology. The issues include short-circuit current and sneak leakage current prevention. Towards validating the proposed techniques, a Personal Digital Assistant (PDA) processor has been implemented using the methodology, and a 0.18um process. The fabricated PDA processor operates at 333MHz which has been improved about 23% at no additional cost of redesign and masks, and consumes about 2uW of standby mode leakage power which could have been three orders of magnitude larger if the MTCMOS technology was not applied.

새로운 능동형 커먼 모드 전압 감쇄기를 이용한 고주파 누설전류 억제 (The suppression of high frequency leakage current using a new active Common Mode Voltage Damper)

  • 구정회;빈재구;박성준;김철우
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2001년도 전력전자학술대회 논문집
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    • pp.151-154
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    • 2001
  • This paper propose a new active common-mode voltage damper circuit that is capable of suppressing a common-mode voltage produced in the PWM VSI. The new active common mode voltage damper is consisted of a half-bridge inverter and a common mode transformer with a blocking capacitor. Principle of the active common mode damper is as follow; by applying the compensation voltage which has the same amplitude and opposite polarity to the PWM inverter system. So, common mode voltage and high frequency leakage current can be reduced. Simulated and experimental results show that common-mode voltage damper makes contributions to reducing a high frequency leakage current and common-mode voltage.

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A Leakage-Based Solution for Interference Alignment in MIMO Interference Channel Networks

  • Shrestha, Robin;Bae, Insan;Kim, Jae Moung
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제8권2호
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    • pp.424-442
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    • 2014
  • Most recent research on iterative solutions for interference alignment (IA) presents solutions assuming channel reciprocity based on the suppression of interference from undesired sources by using an appropriate decoding matrix also known as a receiver combining matrix for multiple input multiple output (MIMO) interference channel networks and reciprocal networks. In this paper, we present an alternative solution for IA by designing precoding and decoding matrices based on the concept of signal leakage (the measure of signal power that leaks to unintended users) on each transmit side. We propose an iterative algorithm for an IA solution based on maximization of the signal-to-leakage-and-noise ratio (SLNR) of the transmitted signal from each transmitter. In order to make an algorithm removing the requirement of channel reciprocity, we deploy maximization of the signal-to-interference-and-noise ratio (SINR) in the design of the decoding matrices. We show through simulation that minimizing the leakage in each transmission can help achieve enhanced performance in terms of aggregate sum capacity in the system.

이미지 신호를 이용한 원자력발전소 강재배관 Tee의 저주기 피로 거동 (Low-cycle Fatigue Behaviors of the Steel Pipe Tee of a Nuclear Power Plant Using Image Signals)

  • 김성완;전법규;정진환;김성도
    • 한국구조물진단유지관리공학회 논문집
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    • 제23권6호
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    • pp.77-83
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    • 2019
  • 원자력발전소에 지진격리장치를 설치하면 지진에 의한 하중을 지진격리장치가 담당하면서 설치 전보다 큰 변위가 발생하게 될 것으로 예상되며, 변위증가에 따라 일부 설비의 지진리스크가 증가될 가능성이 있다. 특히 지진격리된 구조물과 일반 구조물을 연결하는 설비인 배관 시스템의 경우 지진리스크가 크게 증가될 것으로 예상된다. 본 연구에서는 원자력발전소 배관 시스템의 취약부위인 강재 배관 Tee의 한계상태를 누수로 정의하고 면내반복가력시험을 수행하였다. 강재 배관 Tee의 모멘트와 변형각은 기존의 센서를 이용한 계측이 어려우므로 이미지 신호를 이용하여 측정하였다. 본 연구에서는 3인치 강재 배관 Tee의 모멘트와 변형각의 관계를 이용한 누수 선도 및 저주기 피로 곡선들을 제시하였다.

닫힌 공간에서의 광역배관 누출 감시를 위한 배열센서를 이용한 누설 위치 검출 (Leakage Localization with an Acoustic Array that Covers a Wide Area for Pipeline Leakage Monitoring in a Closed Space)

  • 박춘수;전종훈;박진호
    • 비파괴검사학회지
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    • 제33권5호
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    • pp.422-429
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    • 2013
  • 배관에서 발생한 문제는 비단 배관의 손상뿐만 아니라, 배관과 연결된 주요기기 혹은 시스템 전체의 작동에도 영향을 주기 때문에 이상 유무에 대한 감시가 필요하다. 특히, 원전 2차계통의 배관들은 안전상의 이유로 넓은 실내 공간 내에 복잡하게 배치되어 있다. 넓은 영역에 배치되어 있는 전체 배관의 누출 상태 감시를 하기 위해서는 센서 배열을 이용한 원격지에서의 누출 감시 방법이 효율적인데, 닫힌 공간 내에 있기 때문에 발생하는 반사파의 영향을 고려하여야 한다. 따라서 복잡한 실내 공간에서 발생하는 반사파의 특성과 빔형성법에의 영향을 수학적으로 살펴보았다. 그리고 반사파의 영향을 줄이는 공간평균방법을 적용한 빔형성법을 사용하여 광역배관의 구조 건전성 감시가 가능한 방법에 대해 제안하고, 이를 모사한 전산 모의실험과 누출 배관의 축소 모형 장치를 이용한 실험을 통하여 그 적용성을 검증하였다.