• IE interfaces
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• v.16 no.spc
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• pp.14-20
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• 2003

This paper presents a multi-criteria decision model and Multi-Criteria Generic Algorithm(MCGA) approach to improve backbone topology by leveraging the Virtual Link(VL) system in an hierarchical Link-State(LS) routing domain. Given that the sound backbone topology structure has a great impact on the overall routing performance in an hierarchical LS domain, the importance of this research is evident. The proposed decision model is to find an optimal configuration of VLs that properly meets two-pronged engineering goals in installing and maintaining VLs: i.e., operational costs and network reliability. The experiment results clearly indicates that it is essential to the effective operations of hierarchical LS routing domain to consider not only engineering aspects but also specific benefits from systematical layout of VLs, thereby presenting the validity of the decision model and MCGA.

• Proceedings of the Safety Management and Science Conference
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• 2008.11a
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• pp.649-658
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• 2008

This paper investigates the optimal nesting system for a board. A hybrid method is used to search the optimal solution for rectangular nesting problem. This method is composed of heuristic approach algorithm. An engineer's experience of board nesting in which a loss occurred to sheet because of various individual error and diffidence. So, item layout at resource sheet were evaluated in engineering algorithm logic in which specially designed was installed. The nesting system consists of Lisp and Visual Basic. The system was controlled by AutoCAD so as to best item batch path test.

• Journal of Korean Association for Spatial Structures
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• v.21 no.2
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• pp.89-97
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• 2021

This paper describes an adaptive hybrid evolutionary firefly algorithm for a topology optimization of truss structures. The truss topology optimization problems begins with a ground structure which is composed of all possible nodes and members. The optimization process aims to find the optimum layout of the truss members. The hybrid metaheuristics are then used to minimize the objective functions subjected to static or dynamic constraints. Several numerical examples are examined for the validity of the present method. The performance results are compared with those of other metaheuristic algorithms.

• Journal of Korean Institute of Industrial Engineers
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• v.5 no.1
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• pp.45-51
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• 1979

This paper presents a heuristic solution procedure for the quadratic assignment problem, ranking procedure, which can handle the case where not all of the facilities have the same size of area. The ranking procedure is found more efficient than two other existing heuristic procedures from results of computational experience. Based on the out-patients flow pattern and the procedure developed, an improved layout of the three existing general hospitals is developed with the objective of minimizing the total distance travelled by patients in the central and the out-patient clinic.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.739-742
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• 2006

In this paper, we propose a method for automatic generation of equivalent circuit for unit cell of LCDTV. In order to extract a circuit model, computer program generates electrical connectivity of resistors and capacitors from the layout through pattern analysis with electrode and port information. For combining two types of independent equivalent circuits, we propose a node insertion algorithm. As a consequence, we can generate an equivalent RC circuit without increasing the capacitive elements.

• Journal of Electrical Engineering and information Science
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• v.3 no.2
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• pp.139-144
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• 1998

This paper describes the design of a variable rate QPSK demodulator for digital satellite TV system. This true variable-rate demodulator employs a unique architecture to realize an all digital synchronization and detection algorithm. Data-flow based design approach enabled a seamless transition from high level design optimization to physical layout. The demodulator has been integrated with Viterbi decoder, de-interleaver, and Ree-Solomon decoder to make a single chip Digital Video Broadcast (DVB) receiver. The receiver IC has been fabricated with a 0.5mm CMOS TLM process and proved fully functional in a real-world set-up.

• Transactions of the Korean Society of Pressure Vessels and Piping
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• v.19 no.2
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• pp.93-101
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• 2023

In this study, a deep learning algorithm was used to diagnose electric potential signals obtained through CIPS and DCVG, used indirect inspection methods to confirm the soundness of buried pipes. The deep learning algorithm consisted of CNN(Convolutional Neural Network) model for diagnosing the electric potential signal and Grad CAM(Gradient-weighted Class Activation Mapping) for showing the flaw prediction point. The CNN model for diagnosing electric potential signals classifies input data as normal/abnormal according to the presence or absence of flaw in the buried pipe, and for abnormal data, Grad CAM generates a heat map that visualizes the flaw prediction part of the buried pipe. The CIPS/DCVG signal and piping layout obtained from the 3D finite element model were used as input data for learning the CNN. The trained CNN classified the normal/abnormal data with 93% accuracy, and the Grad-CAM predicted flaws point with an average error of 2m. As a result, it confirmed that the electric potential signal of buried pipe can be diagnosed using a CNN-based deep learning algorithm.

• Korean Journal of Construction Engineering and Management
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• v.12 no.1
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• pp.43-52
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• 2011

Unnecessary transportation of resources are one of the major causes that adversely affect construction site work productivity. Therefore, layout related studies have been conducted with efforts to develop management technologies and techniques to minimize the resource transportation made at site-level. However, although the necessity for floor-level layout planning studies has been increasing as buildings have become larger and floors have become more complicated, studies to optimize the transportation of materials inside buildings are currently not being actively conducted. Therefore, in this study, a model was developed using genetic algorithms(GA) that will enable the optimization of the locations of finishing materials on the work-floor. With the established model, the arrangement of diverse materials on complicated floors can be planned and the optimized material layout planning derived from the model can minimize the total material transportation time spent by laborers during their working day. In addition, to calculate travel distances between work sites and materials realistically, the concept of actual travel distances was applied. To identify the applicability of the developed model and compare it with existing methodologies and analyze it, the model was applied to actual high-rise residential complexes.

• The KIPS Transactions:PartA
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• v.16A no.2
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• pp.101-112
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• 2009

Existing techniques for defragmentation of the file system need intensive disk operation for some periods at specific time such as disk defragmentation program. In this paper, for solving this problem, we design and implement the automatic and continuous defragmentation free system by distributing the disk operation. We propose the Automatic Layout Scoring(ALS) mechanism for measuring defragmentation degree and suggest the Lazy Copy mechanism that copies the defragmented data at idle time for scattering the disk operation. We search the defragmented file by Automatic Layout Scoring mechanism and then find for empty spaces for that searched file. After lazy copy of searched fils to empty space for preventing that file from being lost, the algorithm solves the defragmentation problem by updating the I-node of that file. We implement these algorithms in Linux and evaluate them for small and defragmented file to get the layout scoring. We outperform the Linux EXT2 file system by $2.4%{\sim}10.4%$ in layout scoring evaluation. And the performance of read and write for various file size is better than the EXT2 by $1%{\sim}8.5%$ for write performance and by $1.2%{\sim}7.5%$ for read performance. We suggest this system for solving the problem of defragmentation automatically without disturbing the I/O task and manual management.

• The KIPS Transactions:PartA
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• v.12A no.3 s.93
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• pp.215-222
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• 2005

The efficient utilization of cache memories is a key factor in achieving high performance for computing large signal transforms. Nonunit stride access in computation of large DFTs causes cache conflict misses, thereby resulting in poor cache performance. It leads to a severe degradation in overall performance. In this paper, we propose a dynamic data layout approach considering the memory hierarchy system. In our approach, data reorganization is performed between computation stages to reduce the number of cache misses. Also, we develop an efficient search algorithm to determine the optimal tree with the minimum execution time among possible factorization trees considering the size of DFTs and the data access stride. Our approach is applied to compute the fast Fourier Transform (FFT). Experiments were performed on Pentium 4, $Athlon^{TM}$ 64, Alpha 21264, UtraSPARC III. Experiment results show that our FFT achieve performance improvement of up to 3.37 times better than the previous FFT packages.