• Journal of information and communication convergence engineering
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• 제19권2호
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• pp.114-119
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• 2021

This paper proposes a method to find an optimal T' with the most terminal of the subset of T' trees that can be connected by a given length by improving a memetic genetic algorithm within several constraints, when the set of terminal T is given to the Euclidean plane R². Constraint (1) is that a given length cannot connect all terminals of T, and (2) considers only the rectilinear layout of the edge connecting each terminal. The construction of interconnections has been used in various design-related areas, from network to architecture. Among these areas, there are cases where only the rectilinear layout is considered, such as wiring paths in the computer network and VLSI design, network design, and circuit connection length estimation in standard cell deployment. Therefore, the heuristics proposed in this paper are expected to provide various cost savings in the rectilinear layout.

• 국제학술발표논문집
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• The 9th International Conference on Construction Engineering and Project Management
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• pp.312-318
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• 2022

Robot-based layout automation has been recently promoted for the purpose of improving productivity and quality. Marking robots have various functional demands to secure marking precision and environmental adaptability. In particular, in order to automate marking work of building structure, correction of the marking line through position recognition of rebars placed is required. Because the rebars must maintain a constant cover thickness from the formwork surface, if the rebars are out of planned position, the rebar or marking line need to be corrected to secure the cover thickness. Thus, the marking robot for structural work needs to have the function for determining the position correction of the rebar or the marking line. In order to judge the correction of marking line, it is required to measure the distance between the planned marking line and the rebar placed. Therefore, this study proposes an algorithm that can measure the distance between the planned line and the rebar, and correct marking line for the automatic operation of the marking robot. The results of this study will be utilized as a core function for unmanned operation of the marking robot and contribute to securing precise marking by reflecting construction errors.

• 대한산업공학회지
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• 제19권3호
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• pp.51-57
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• 1993

This paper develops 0($n^3$) algorithm to construct a cut-tree generated by Gomory-Hu algorithm. The algorithm only requires node sets defined by the minimal cut in each of the (n-1) maximal flow determinations. Merging computerized facility layout procedure that uses cut-tree concept to generate design skeletons with our algorithm requires less storage space than merging it with Gomory-Hu algorithm. Also, the cut-tree can easily be modified when the (n-1) minimal cut-sets are updated due to changes on arc capacities.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.329-332
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• 2001

This paper proposes a capacitance extraction algorithm based on boundary element method and describes the implemented 2-dimension extractor based on the proposed algorithm. The proposed algorithm uses a generalized conjugate residual iterative algorithm with a hierarchical subdivision. The implemented 2-D extractor computes the capacitances of complicated 2-D geometry of ideal conductors in uniform dielectric and can be efficiently used in the VLSI layout designs due to its user-friendly GUI.

• 정보처리학회논문지:컴퓨터 및 통신 시스템
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• 제2권2호
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• pp.59-66
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• 2013

본 논문에서는 임베디드 시스템에서 DSP를 위한 메모리 접근 변수의 저장 방법에 대한 최적화 ILP 알고리즘을 제안하였다. 본 논문은 0-1 ILP 공식을 이용하여 DSP 주소 생성 유닛의 메모리 변수 데이터 레이아웃을 최소화한다. 제약 조건을 기반으로 변수의 메모리 할당 여부를 식별하고, 변수가 지시하는 주소코드를 프로그램 포인터에 등록한다. 프로그램의 처리 순서가 프로그램 포인터에 선언되면, 해당 변수의 주소코드에 대한 자동증감 모드를 적용한다. 주소 레지스터에 대한 로드를 최소화하여 변수의 데이터 레이아웃을 최적화한다. 본 논문에서 제안한 알고리즘의 효율성을 입증하기 위하여 FICO Xpress-MP Modeling Tools을 이용하여 벤치마크에 적용하였다. 벤치마크 적용 결과, 기존의 선언적 주문 메모리 레이아웃보다 제안한 알고리즘을 적용한 최적의 메모리 레이아웃이 주소/수정 레지스터에 대한 로드 수를 감소시켰고, 주소코드의 접근을 줄임으로써, 프로그램의 실행 시간을 단축시켰다.

• 대한전자공학회논문지
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• 제24권6호
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• pp.1087-1094
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• 1987

In this paper, we describe about polygon resizing porblem where the given polygons are expanded or shrunk in two dimensional plane. First, the definition of polygon resizing and it's problems are given, then the enhanced XY method is proposed: the polygon resizing can be completed in one directional sweep of plane only, usisng enhanced plane sweep method. The time complexity is 0(n log n), and space complexity 0(\ulcorner), where n is the number of verties of polygons. The applications of polygon resizing to the mask artwork processing and layout verification are discussed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1463-1466
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• 1987

The problem of generating minimal area CMOS functional cell layout can be converted to that of decomposing the transistor connection graph into a minimum number of subgraphs, each having a pair of Euler paths with the same sequence of input labels on the N-graph and P-graph, which are portions of the graph corresponding to NMOS and PMOS parts respectively. This paper proposes a heuristic algorithm which yields a nearly minimal number of Euler paths from the path representation formula which represents the give a logic function. Subpath merging is done through a list processing scheme where the pair of paths which results in the lowest cost is successively merged from all candidate merge pairs until no further path merging and further reduction of number of subgraphs are possible. Two examples were shown where we were able to further reduce the number of interlaces, i.e., the number of non-butting diffusion islands, from 3 to 2, and from 2 to 1, compared to the earlier work [1].

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.1098-1100
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• 2005

The floorplanning problem is an essential design step in VLSI layout design and it is how to place rectangular modules as density as possible. And then, as the DSM advances, the VLSI chip becomes more congested even though more metal layers are used for routing. Usually, a VLSI chip includes several buses. As design increases in complexity, bus routing becomes a heavy task. To ease bus routing and avoid unnecessary iterations in physical design, we need to consider bus planning in early floorplanning stage. In this paper, we propose a floorplanning method for topological constraint consisting of bus constraint and memory constraint. The proposed algorithms based on Genetic Algorithm(GA) is adopted a sequence pair. For selection control, new objective functions are introduced for topological constraint. Studies on floor planning and cell placement have been reported as being applications of GA to the LSI layout problem. However, no studies have ever seen the effect of applying GA in consideration of topological constraint. Experimental results show improvement of bus and memory constraint.

• 대한전자공학회논문지
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• 제24권2호
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• pp.355-361
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• 1987

The shuffle-exchange graph is known as a structure to perform the parallel algorithms like Discrete Fourier Transform(DFT), matrix multiplication and sorting. In this paper, the layout for the shuffle-exchange graph is described and this layout places emphasis on the placement of nodes that has the capability to have as small area as possible, have as a small number of crossings as possible, and have as short wires as possible. The algorithm corrdsponding these conditions is proposed and each evaluation factor and the placement of the N-node shuffle-exchange graph is performed with FORTRAN and BASIC program, and these results are calcualted.

• 한국CDE학회논문집
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• 제9권2호
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• pp.102-111
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• 2004

In this paper, the efficient layout method for generating common and continuous cutting path of flat-bar profile. The ‘flat -bar’ is a stiffener and has long rectangular shape. This paper describes a fast nesting algorithm of the flat-bar, and a procedure to generate cutting path of gas/plasma torch, which is operated by a NC (numerically controlled) gas/plasma cutting machine. By using this common and continuous path, the machining-time for cutting and the maintenance-cost of plasma-torch could be reduced. Proposed procedures are written in C-language and applied to the Interactive Flat-Bar-Nesting System executable on Open VMS with X-Window system.