• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.2
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• pp.259-265
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• 2012

Recently, many research works are focusing on DVC (Distributed Video Coding) system for low complexity encoder. Most DVC systems need feedback channel for parity bit control to achieve the good RD performances, however, this causes the system to have high decoding latency and is considered as one of the most critical problems for real implementation. In order to overcome this problem, this paper proposes an effective distributed video decoding method using adaptive LDPCA frame-based parity bit request estimation. The proposed method applies for the pixel-domain Wyner-Ziv system and exploits the statistical characteristics between adjacent LDPCA frames to estimate adaptively the parity bit request. Through computer simulations, it is shown that the proposed method achieves about 80% of latency reduction compared to the conventional no-estimation DVC system.

• Journal of Audiology & Otology
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• v.24 no.1
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• pp.10-16
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• 2020

Background and Objectives:The blockage of adenosine receptors by caffeine changes the levels of neurotransmitters. These receptors are present in all parts of the body, including the auditory and vestibular systems. This study aimed to evaluate the effect of caffeine on evoked potentials using auditory brainstem responses (ABRs) and cervical vestibular-evoked myogenic potentials (cVEMPs) in a double-blind placebo-controlled study. Subjects and Methods: Forty individuals (20 females and 20 males; aged 18-25 years) were randomly assigned to two groups: the test group (consuming 3 mg/kg pure caffeine powder with little sugar and dry milk in 100 mL of water), and the placebo group (consuming only sugar and dry milk in 100 mL water as placebo). The cVEMPs and ABRs were recorded before and after caffeine or placebo intake. Results: A significant difference was observed in the absolute latencies of I and III (p<0.010), and V (p<0.001) and in the inter-peak latencies of III-V and I-V (p<0.001) of ABRs wave. In contrast, no significant difference was found in cVEMP parameters (P13 and N23 latency, threshold, P13-N23 amplitude, and amplitude ratio). The mean amplitudes of P13-N23 showed an increase after caffeine ingestion. However, this was not significant compared with the placebo group (p>0.050). Conclusions: It seems that the extent of caffeine's effects varies for differently evoked potentials. Latency reduction in ABRs indicates that caffeine improves transmission in the central brain auditory pathways. However, different effects of caffeine on auditory- and vestibular-evoked potentials could be attributed to the differences in sensitivities of the ABR and cVEMP tests.

• Korean Journal of Audiology
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• v.24 no.1
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• pp.10-16
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• 2020

Background and Objectives:The blockage of adenosine receptors by caffeine changes the levels of neurotransmitters. These receptors are present in all parts of the body, including the auditory and vestibular systems. This study aimed to evaluate the effect of caffeine on evoked potentials using auditory brainstem responses (ABRs) and cervical vestibular-evoked myogenic potentials (cVEMPs) in a double-blind placebo-controlled study. Subjects and Methods: Forty individuals (20 females and 20 males; aged 18-25 years) were randomly assigned to two groups: the test group (consuming 3 mg/kg pure caffeine powder with little sugar and dry milk in 100 mL of water), and the placebo group (consuming only sugar and dry milk in 100 mL water as placebo). The cVEMPs and ABRs were recorded before and after caffeine or placebo intake. Results: A significant difference was observed in the absolute latencies of I and III (p<0.010), and V (p<0.001) and in the inter-peak latencies of III-V and I-V (p<0.001) of ABRs wave. In contrast, no significant difference was found in cVEMP parameters (P13 and N23 latency, threshold, P13-N23 amplitude, and amplitude ratio). The mean amplitudes of P13-N23 showed an increase after caffeine ingestion. However, this was not significant compared with the placebo group (p>0.050). Conclusions: It seems that the extent of caffeine's effects varies for differently evoked potentials. Latency reduction in ABRs indicates that caffeine improves transmission in the central brain auditory pathways. However, different effects of caffeine on auditory- and vestibular-evoked potentials could be attributed to the differences in sensitivities of the ABR and cVEMP tests.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.17 no.3
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• pp.166-175
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• 2024

In this paper, the Window-Masking Method and HAT (Hardware Attached Top) CPU SoM (System on Module) are used to improve the performance and reduce the weight of the MANET (Mobile Ad-hoc Network) network synchronization system using time division redundancy. We propose converting it into a RISC-V based soft-core MCU and mounting it on an FPGA, a hardware accelerator. It was also verified through experiment. In terms of performance, by applying the proposed technique, the synchronization acquisition range is from -50dBm to +10dBm to -60dBm to +10dBm, the lowest input level for synchronization is increased by 20% from -50dBm to -60dBm, and the detection delay (Latency) is 220ns. Reduced by 43% to 125ns. In terms of weight reduction, computing resources (48%), size (33%), and weight (27%) were reduced by an average of 36% by replacing with soft-core MCU.

• Journal of Korea Society of Digital Industry and Information Management
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• v.16 no.2
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• Journal of information and communication convergence engineering
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• v.14 no.2
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• pp.89-96
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• 2016

In mobile communication, there are various types of handoff for the support of all forms of mobility. Proxy mobile IPv6 (PMIPv6) enables local network-based mobility management of a mobile node without any effect of mobility-related signaling. Recently, PMIPv6 has been considered for supporting mobility management in LTE/SAE-based mobile networks. To support seamless mobility in heterogeneous mobile networks, the overall cost of handoffs needs to be minimized and the procedure should be guaranteed to be secure. However, the reduction of the authentication cost has not been fully investigated to provide seamless connectivity when mobile users perform a handoff between the PMIPv6 domains. This paper proposes secure pre-authentication schemes, completing an authentication procedure before performing a handoff, for a fast handoff in PMIPv6. Analytic models have been used for measuring the authentication latency and for the overhead cost analysis. In addition to providing fast authentication, the proposed pre-authentication schemes can prevent threats such as replay attacks and key exposure.

• ETRI Journal
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• v.34 no.1
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• pp.122-125
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• 2012

A video signal through a high-density optical link has been demonstrated to show the reliability of optical link for high-data-rate transmission. To reduce optical point-to-point links, an electrical link has been utilized for control and clock signaling. The latency and flicker with background noise occurred during the transferring of data across the optical link due to electrical-to-optical with optical-to-electrical conversions. The proposed synchronization technology combined with a flicker and denoising algorithm has given good results and can be applied in high-definition serial data interface (HD-SDI), ultra-HD-SDI, and HD multimedia interface transmission system applications.

• Journal of information and communication convergence engineering
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• v.15 no.4
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• pp.212-216
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• 2017

In this paper, we introduce novel techniques to improve the high performance of AE functions on modern high-end IoT platforms (ARM-NEON), which support SIMD and cryptography instruction sets. For the Sophie Germain Counter Mode of operation (SGCM), counter modes of encryption and prime field multiplication are required. We chose the Montgomery multiplication for modular multiplication. We perform Montgomery multiplication in a parallel way by exploiting both the ARM and NEON instruction sets. Specifically, the NEON instruction performed 128-bit integer multiplication and the ARM instruction performed Montgomery reduction, simultaneously. This approach hides the latency for ARM in the NEON instruction set. For a high-speed counter mode of encryptions for both AE functions, we introduced two-level computations. When the tasks were large volume, we switched to the NEON instruction to execute the encryption operations. Otherwise, we performed the encryptions on the ARM module.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.4C
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• pp.379-388
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• 2007

In this paper, we propose an adaptive turbo decoding algorithm for high order modulation scheme combined with originally design for a standard rate-1/2 turbo decoder for B/QPSK modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/QPSK turbo decoder without any modifications. Adaptive turbo decoder process the received symbols recursively to improve the performance. As the number of iterations increase, the execution time and power consumption also increase as well. The source of the latency and power consumption reduction is from the combination of the radix-4, dual-path processing, parallel decoding, and early-stop algorithms. We implemented the proposed scheme on a field-programmable gate array (FPGA) and compared its decoding speed with that of a conventional decoder. From the result of implementation, we confirm that the decoding speed of proposed adaptive decoding is faster than conventional scheme by 6.4 times.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.465-472
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• 2013

This paper presents a low-complexity triple-error-correcting parallel Bose-Chaudhuri-Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-by-step (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multi-parallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4-parallel (1020, 990) BCH decoder over GF($2^{12}$), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.