• 제목/요약/키워드: latency reduction

검색결과 152건 처리시간 0.027초

Latency Analysis of AVB Network and Optimization Design for Automotive

  • An, Byoungman;Kim, YoungSeop
    • Journal of the Semiconductor & Display Technology
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    • 제18권3호
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    • pp.127-132
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    • 2019
  • This paper presents an overview of automotive communication technologies, including related technology developments. We describe the latency of Audio Video Bridge (AVB) network as well as purpose the optimized design of the Ethernet network system for automotive. Our design plays a significant role in reducing the delay between components. The proposed approach on realistic test cases showed that there was a delay reduction, approximately 49.4%. It is expected that the optimization method for the actual automotive environment can greatly shorten the time period in the design and development process. The results obtained from the experiments on the delay time present in each function are reliable because average values are obtained through repeated actual tests for several months. It will greatly benefit the industry since analyzing the latency between each function in a short period of time is very important.

Buffer Policy based on High-capacity Hybrid Memories for Latency Reduction of Read/Write Operations in High-performance SSD Systems

  • Kim, Sungho;Hwang, Sang-Ho;Lee, Myungsub;Kwak, Jong Wook;Park, Chang-Hyeon
    • Journal of the Korea Society of Computer and Information
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    • 제24권7호
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    • pp.1-8
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    • 2019
  • Recently, an SSD with hybrid buffer memories is actively researching to reduce the overall latency in server computing systems. However, existing hybrid buffer policies caused many swapping operations in pages because it did not consider the overall latency such as read/write operations of flash chips in the SSD. This paper proposes the clock with hybrid buffer memories (CLOCK-HBM) for a new hybrid buffer policy in the SSD with server computing systems. The CLOCK-HBM constructs new policies based on unique characteristics in both DRAM buffer and NVMs buffer for reducing the number of swapping operations in the SSD. In experimental results, the CLOCK-HBM reduced the number of swapping operations in the SSD by 43.5% on average, compared with LRU, CLOCK, and CLOCK-DNV.

An Energy Optimization Technique for Latency and Quality Constrained Video Applications (지연 시간 및 화질 제약이 있는 비디오 응용을 위한 에너지 최적화 기법)

  • 임채석;하순회
    • Journal of KIISE:Computer Systems and Theory
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    • 제31권10호
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    • pp.543-552
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    • 2004
  • This paper proposes an energy optimization technique for latency and quality constrained video applications. It consists of two key techniques: frame-skipping technique and buffering technique. While buffering increases the slack time utilization at the OS level. frame skipping Increases the slack time itself at the application level, and both enhance the effectiveness of the dynamic voltage scaling technique. We use an H.263 encoder application as a test vehicle to which the proposed technique is applied. Experiments demonstrate that the proposed technique achieves noticeable energy reduction satisfying the given latency and video quality constraints.

Content-Aware D2D Caching for Reducing Visiting Latency in Virtualized Cellular Networks

  • Sun, Guolin;Al-Ward, Hisham;Boateng, Gordon Owusu;Jiang, Wei
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제13권2호
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    • pp.514-535
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    • 2019
  • Information-centric networks operate under the assumption that all network components have built-in caching capabilities. Integrating the caching strategies of information centric networking (ICN) with wireless virtualization improves the gain of virtual infrastructure content caching. In this paper, we propose a framework for software-defined information centric virtualized wireless device-to-device (D2D) networks. Enabling D2D communications in virtualized ICN increases the spectral efficiency due to reuse and proximity gains while the software-defined network (SDN) as a platform also simplifies the computational overhead. In this framework, we propose a joint virtual resource and cache allocation solution for latency-sensitive applications in the next-generation cellular networks. As the formulated problem is NP-hard, we design low-complexity heuristic algorithms which are intuitive and efficient. In our proposed framework, different services can share a pool of infrastructure items. We evaluate our proposed framework and algorithm through extensive simulations. The results demonstrate significant improvements in terms of visiting latency, end user QoE, InP resource utilization and MVNO utility gain.

An Energy Efficient and Low Latency MAC Protocol Using RTS Aggregation for Wireless Sensor Networks (무선 센서 네트워크에서 RTS 통합을 이용한 에너지 효율성과 낮은 지연을 갖는 MAC 프로토콜)

  • Lee, Dong-Ho;Chung, Kwang-Sue
    • Journal of KIISE:Information Networking
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    • 제35권4호
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    • pp.326-336
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    • 2008
  • Wireless sensor networks have been studied with two typical applications called event-driven and periodic monitoring. Although these applications have different core requirements, they have the same low latency requirement. However, main issue of the protocol in wireless sensor networks was focused on an energy efficiency, so it has not considered the latency problem. In this paper, we propose the RA-MAC, an energy efficient and low latency MAC protocol using a new channel access mechanism and the RTS Aggregation scheme for wireless sensor networks. Our simulation results show that the RA-MAC provides energy savings and latency reduction.

A Latency Optimization Mapping Algorithm for Hybrid Optical Network-on-Chip (하이브리드 광학 네트워크-온-칩에서 지연 시간 최적화를 위한 매핑 알고리즘)

  • Lee, Jae Hun;Li, Chang Lin;Han, Tae Hee
    • Journal of the Institute of Electronics and Information Engineers
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    • 제50권7호
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    • pp.131-139
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    • 2013
  • To overcome the limitations in performance and power consumption of traditional electrical interconnection based network-on-chips (NoCs), a hybrid optical network-on-chip (HONoC) architecture using optical interconnects is emerging. However, the HONoC architecture should use circuit-switching scheme owing to the overhead by optical devices, which worsens the latency unfairness problem caused by frequent path collisions. This resultingly exert a bad influence in overall performance of the system. In this paper, we propose a new task mapping algorithm for optimizing latency by reducing path collisions. The proposed algorithm allocates a task to a certain processing element (PE) for the purpose of minimizing path collisions and worst case latencies. Compared to the random mapping technique and the bandwidth-constrained mapping technique, simulation results show the reduction in latency by 43% and 61% in average for each $4{\times}4$ and $8{\times}8$ mesh topology, respectively.

Reduction of Read Access Latency by Invalid Hint in Directory-Based Cache Coherence Scheme (디렉토리를 이용한 캐쉬 일관성 유지 기법에서 무효화 힌트를 이용한 읽기 접근 시간 감소)

  • Oh, Seung-Taek;Rhee, Yun-Seok;Maeng, Seung-Ryoul;Lee, Joon-Won
    • Journal of KIISE:Computer Systems and Theory
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    • 제27권4호
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    • pp.408-415
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    • 2000
  • Large scale shared memory multiprocessors have suffered from large access latency to shared memory. The large latency partially stems from a feature of directory-based cache coherence schemes which require a shared memory access to be serviced at a home node of the memory block. The home visit results in three or more hops traversal for a memory read access. The traversal becomes much longer as a system scales up. In this paper, we propose a new cache coherence scheme that reduces read access latency. The proposed scheme exploits ideas of invalid hint. Invalid hint for a cache block means which node has invalidated the cache block before. Thus a read access request can be directly sent to and serviced by the node (called owner) without help of a home node. Execution-driven simulation is employed to evaluate performance of the proposed scheme. The simulation results show that read access latency and execution time are reduced.

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Topology Design for Energy/Latency Optimized Application-specific Hybrid Optical Network-on-Chip (HONoC) (특정 용도 하이브리드 광학 네트워크-온-칩에서의 에너지/응답시간 최적화를 위한 토폴로지 설계 기법)

  • Cui, Di;Lee, Jae Hoon;Kim, Hyun Joong;Han, Tae Hee
    • Journal of the Institute of Electronics and Information Engineers
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    • 제51권11호
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    • pp.83-93
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    • 2014
  • It is a widespread concern that electrical interconnection based network-on-chip (NoC) will ultimately face the limitation in communication bandwidth, transmission latency and power consumption in the near future. With the development of silicon photonics technology, a hybrid optical network-on-chip (HONoC) which embraces both electrical- and optical interconnect, is emerging as a promising solution to overcome these problems. Today's leading edge systems-on-chips (SoCs) comprise heterogeneous many-cores for higher energy efficiency, therefore, extended study beyond regular topology based NoC is required. This paper proposes an energy and latency optimization topology design technique for HONoC taking into account the traffic characteristics of target applications. The proposed technique is implemented with genetic algorithm and simulation results show the reduction by 13.84% in power loss and 28.14% in average latency, respectively.

An improvement of Medium Access Control Protocol in Ubiquitous Sensor Networks (유비쿼터스 센서 네트워크의 매체 접근 제어 기법에 대한 개선 방안)

  • Jang, Ho;Lee, Myung-Sub;Jeon, Woo-Sang
    • The KIPS Transactions:PartC
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    • 제16C권3호
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    • pp.373-382
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    • 2009
  • we present more efficient method of a medium access for real-time ubiquitous sensor networks. Proposed MAC protocol is like the randomized CSMA/CA protocol, but unlike previous legacy protocols, it does not use a time-varying contention window from which a node randomly picks a transmission slot. To reduce the latency for the delivery of event reports from sensor nodes, we carefully decide to select a fixed-size contention window with non-uniform probability distribution of transmitting in each slot. We show that the proposed method can offer up to several times latency reduction compared to legacy of IEEE 802.11 as the size of the sensor network scales up to 256 nodes using a widely-used network simulation package, NS-2. We finally show that proposed MAC scheme comes close to meet bounds on the best latency being achieved by a decentralized CSMA-based MAC protocol for real-time ubiquitous sensor networks which is sensitive to latency.

Implementation of a DI Multi-Touch Display Using an Improved Touch-Points Detection and Gesture Recognition (개선된 터치점 검출과 제스쳐 인식에 의한 DI 멀티터치 디스플레이 구현)

  • Lee, Woo-Beom
    • Journal of the Institute of Convergence Signal Processing
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    • 제11권1호
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    • pp.13-18
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    • 2010
  • Most of the research in the multi-touch area is based on the FTIR(Frustrated Total Internal Re리ection), which is just implemented by using the previous approach. Moreover, there are not the software solutions to improve a performance in the multi touch-blobs detection or the user gesture recognition. Therefore, we implement a multi-touch table-top display that is based on the DI(Diffused Illumination), the improved touch-points detection and user gesture recognition. The proposed method supports a simultaneous transformation multi-touch command for objects in the running application. Also, the system latency time is reduced by the proposed ore-testing method in the multi touch-blobs detection processing. Implemented device is simulated by programming the Flash AS3 application in the TUIO(Tangible User Interface Object) environment that is based on the OSC(Open Sound Control) protocol. As a result, Our system shows the 37% system latency reduction, and is successful in the multi-touch gestures recognition.