• The Transactions of the Korean Institute of Electrical Engineers
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• v.44 no.2
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• pp.222-227
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• 1995

A new IGBT structure, which may suppress latch-up phenomena considerably, is proposed and verified by MEDICI simulation. The proposed structure employing the segmented $n^{+}$ buffer layer increases latch-up current capability due to suppression of the current flowing through the resistance of $p^{-}$ well, $R_{p}$, which is the main cause of latch-up phenomena without degradation of forward characteristics. The length of the $n^{+}$ buffer layer is investigated by considering the trade-off between the latch-up current capability and the forward voltage drop. The segmented $N^{+}$ buffer layer results in better latch-up immunity in comparison with the uniform buffer layer.

• Transactions on Electrical and Electronic Materials
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• v.2 no.4
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• pp.30-32
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• 2001

In this paper, a new silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) is proposed to improve the latch-up performance without current path underneath the n$^{+}$ cathode region. The improvement of latch-up performance is verified using the two- dimensional simulator MEDICI and the simulation results on the latch-up current density are 4468 A/cm2 for the proposed LIGBT and 1343 A/$\textrm{cm}^2$ for the conventional LIGBT. The proposed SOI LIGBT exhibits 3 times larger latch-up capability than the conventional SOI LIGBT.T.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.11
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• pp.2089-2092
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• 2010

There are many cases that interrupt the production process because of malfunctions caused by electronic circuit boards which control equipment, but it is difficult to distinctly identify the causes in many cases. Especially, CMOS devices with the control logic circuit return automatically to normal state after their own faults. Therefore it is not easy to analyze the problems with electronic circuit boards. Recently, nuclear power plant experienced a failure due to the malfunction of electronic circuit boards and it was identified that the reason of the malfunction was because of latch-up phenomenon caused by external surge in electronic devices. This paper presents the causes and the phenomenon of latch-up by experiment and also a way using counter EMF diodes, noise filters and surge protective devices to prevent latch-up phenomenon from electronic circuit boards, finally confirms the effectiveness of the result by experiment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.111-118
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• 2008

In this paper, novel latch-up prevention method that employs power-up sequential switches has been proposed to relieve latch-up problem in liquid crystal display (LCD) driver ICs. These sequential switches are inserted in the 2'nd and 3'rd boosting stages, and are used to short the emitter-base terminals of parasitic p-n-p-n circuit before relevant boosting stages are activated during power-up sequence. To verily the performance of the proposed method, test chips were designed and fabricated in a 0.13-um CMOS process technology. The measurement results indicated that, while the conventional LCD driver If entered latch-up mode at $50^{\circ}C$ accompanying a significant amount of excess current, the driver IC adopting the proposed method showed no latch-up phenomenon up to $100^{\circ}C$ and maintained normal current level of 0.9mA.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.11
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• pp.686-689
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• 2014

Electrostatic discharge has been considered as a major reliability problem in the semiconductor industry. ESD reliability is an important issue for these products. Therefore, each I/O (Input/Output) PAD must be designed with a protection circuitry that creates a low impedance discharge path for ESD current. This paper presents a novel Lateral Insulated Gate Bipolar (LIGBT)-based ESD protection circuit with latch-up immunity and high robustness. The proposed circuit is fabricated by using 0.18 um BCD (bipolar-CMOS-DMOS) process. Also, TLP (transmission line pulse) I-V characteristic of proposed circuit is measured. In the result, the proposed ESD protection circuit has latch-up immunity and high robustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristic can be applied to analog integrated circuits.

• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.240-242
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• 1993

A novel structure, which can suppress latch-up phenomena, is proposed and verified by the PISCESIIB simulation. It is shown that this structure employing the selective N+ buffer layer increases latch-up current density due to suppression of the current flowing through the p-body. The width of the N+ buffer layer is optimized considering the trade-off between the latch-up current density and the forward voltage drop. The selective buffer layer results in an improved trade-off relationship compared with the uniform buffer layer.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.1
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• pp.103-110
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• 1995

Trench-Gate SOI LIGBT with improved latch-up capability has been proposed and verified by MEDICI simulation. The new SOI LIGBT exhibits 6 time larger latch-up capability of the new device is almost preserved independent of lifetime. the large latch-up capability of the new SOI LIGBT may be realized due to the fact that the hole current in the new device would bypass through the shorted cathode contact without passing the p-well region under the n+ cathode. Forward voltage drop is increased by 25% when a epi thickness is 6$\mu$m. However, the increase of the forward voltage is negligible when the epi thickness is increased to 10$\mu$m. It is found that the swithcing time of the new device is almost equal to the conventional devices. Evaluated breakdown voltage of proposed SOILIGBT is 250 V and that of the conventional SOI LIGBT is 240 V, where the thickness of the vuried oxide and n- epi is 3$\mu$m and 6$\mu$m, respectively.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.3
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• pp.422-426
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• 2012

Transient radiation is emitted during a nuclear explosion. Transient radiation causes a fatal error in the CMOS circuit as a Upset and Latch-up. In this paper, transient radiation NMOS, PMOS, INVERTER SPICE model was proposed on the basisi of transient radiation effects analysis using TCAD(Technology Computer Aided Design). Photocurrent generated from the MOSFET internal PN junction was expressed to the current source and Latch-up phenomenon in the INVERTER was expressed to parasitic thyristor for the transient radiation SPICE model. For example, the proposed transient radiation SPICE model was applied to CMOS NAND circuit. SPICE simulated characteristics were similar to the TCAD simulation results. Simulation time was reduced to 120 times compared to TCAD simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1603-1610
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• 1999

본 논문은 CMOS의 latch-up 특성을 개선하기 위한 효과적인 mask 설계 방법에 관한 것이다. Mask의 평면구조와 latch-up 파라메타와의 상관관계를 실물 제작에 의한 실험과 컴퓨터 시뮬레이션에 의해 도출하였으며, guard ring의 효과에 대해서도 비교 분석하였다. 실험 결과, 수평구조 바이폴라 트랜지스터의 전류증폭률($\beta$n)이 디자인룰에 반비례하였으며, 수직구조 바이폴라 트랜지스터의 전류증폭률($\beta$n)은 디지인룰과 무관하였다. 스위칭전압과 유지전류는 디자인룰에 비례하였다. Guard ring은 latch-up의 가능성을 줄이는 데 상당한 효과가 있었음이 확인되었으며, Guard ring이 없는 경우에 비하여 전류증폭률의 곱($\beta$n$\beta$n)이 약 31% 감소, 유지전류는 약 25%가 향상됨을 확인하였다.

• Proceedings of the KAIS Fall Conference
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• 2004.11a
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• pp.203-205
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• 2004

A soft error rate neutrons is a growing problem for terrestrial integrated circuits with technology scaling. In the acceleration test with high-density neutron beam, a latch-up prohibits accurate estimations of the soft error rate (SER). This paper presents results of analysis for the latch-up characteristics in the circumstance corresponding to the acceleration SER test for SRAM. Simulation results, using a two-dimensional device simulator, show that the deep p-well structure has better latch-up immunity compared to normal twin and triple well structures. In addition, it is more effective to minimize the distance to ground power compared with controlling a path to the $V_{DD}$ power.