• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1308-1311
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• 2002

We present a low-power MPEG-4 video codec chip capable of delivering high-quality video data in wireless multimedia applications. The discussion will focus on the architectural design techniques for implementing a high-performance video compression/decompression chip at low power architectures. The proposed MPEG-4 video codec can perform 30 frames/s of QCIF or 7.5 frame/s of CIF at 27MHz for 128k∼144kbps. By introducing the efficiently optimized Frame Memory Interface architecture, low power motion estimation and embedded ARM microprocessor and AMBA interface, the proposed MPEG-4 video codec has low power consumption for wireless multimedia applications such as IMT-2000.

• 전기의세계
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• v.51 no.5
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• pp.30-35
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• 2002

• Journal of the KSME
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• v.43 no.2
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• pp.43-47
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• 2003

• Proceedings of the KIEE Conference
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• 1993.07a
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• pp.391-394
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• 1993

The acceleration/deceleration control method and interpolated operating are essential to the servo motor control system. In a few years ago, a floating point DSP chip was used for the purpose of processing a lot of calculated amount. But in this paper, we proposed new acceleration/deceleration control method and circular interpolation algorithm without another floating point DSP chip. The validity of proposed algorithms are verified through computer simulation and experimental result.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.449-450
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• 2008

In this paper, we present the design of a system on a chip(SoC) based on Powerline Communication for Power-IT. The SoC deals with power information obtained from analog to digital converter and transmits this data via powerline. We integrate main processor, ADC and PLC function into a chip. Also a FPGA-based emulation system is introduced to evaluate a proposed SoC architecture.

• ETRI Journal
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• v.35 no.5
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• pp.767-774
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• 2013

In this paper, a novel parallel Viterbi decoding scheme is proposed to decrease the decoding latency and power consumption for the software-defined radio (SDR) system. It implements a divide-and-conquer approach by first dividing a block into a series of subblocks, then performing independent Viterbi decoding for each subsequence, and finally merging the surviving subpaths into the final path. Moreover, a network-on-chip-based SDR platform is used to evaluate the performance of the proposed parallel Viterbi decoding scheme. The experiment results show that our scheme can speed up the Viterbi decoding process without increasing the BER, and it performs better than the current state-of-the-art methods.

• 연구논문집
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• s.33
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• pp.17-25
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• 2003

In this work, thermal design of a PCR chip for LOC is systematically conducted. From the numerical simulation of a PCR chip based on the finite volume method, how to control the average temperature of a PCR chip and the temperature difference between the denaturation zone and the annealing zone is presented. The average temperature is shown to be controlled by adjusting heat input and a cooler as well as a heater is shown to be necessary to obtain three individual temperature zones for polymerase chain reaction. To reduce the time required, a heat sink for the cooler is not included in the calculation domain for the PCR chip and heat sink design is conducted separately by using a compact modeling method, the porous medium approach.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.160-166
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• 2012

We performed the development and performance evaluation of reflective type heart rate measurement system for PAPS. We used chip LED and chip photo TR. for low power driving. The measured PPG signal is preprocessed using high pass filter and low pass filter, and the preprocessed signal is displayed by LabVIEW. Also LabVIEW include the algorithm that extract effective signal and calculate the heart rate. We made sure that it will be able to apply to measurement equipment with high accuracy and repetition from exercising subject using this system and algorithm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.542-549
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• 2016

This paper presents a SoC (System-on-a-Chip) dedicated for a single-chip smart capsule which can be used to continuously monitor human alimentary canal pH and temperature values. The SoC is composed of the pH and temperature sensor interface circuit, a wireless transceiver, the power management circuit and the flow control logic. Fabricated in $0.18{\mu}m$ standard CMOS technology, the SoC occupies a die area of ${\sim}9 mm^2$. The SoC consumes 6.15 mW from a 3 V power supply, guaranteeing the smart capsule battery life is no less than 24 hours when using 50 mAh coin batteries. The experimental results show that measurement accuracy of the smart capsule is ${\pm}0.1$ pH and ${\pm}0.2^{\circ}C$ for pH and temperature sensing, respectively, which meets the requirement of in-body pH and temperature monitoring in clinical practice.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.11a
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• pp.3-4
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• 2004

A flexible Packaging scheme, which embedded chip packaging, has been developed using a thinned silicon chip. Mechanical characteristics of thinned silicon chips are examined by bending test and finite element analysis. Thinned silicon chips ($t<50{\mu}m$) are fabricated by chemical etching process to avoid possible surface damages on them. These technologies can be use for a real-time monitoring of blood pressure. Our research targets are implantable blood pressure sensor and its telemetric measurement. By winding round the coronary arteries, we can measure the blood pressure by capacitance variation of blood vessel.