• KSII Transactions on Internet and Information Systems (TIIS)
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• v.17 no.1
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• pp.165-184
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• 2023

The ARX-based lightweight block cipher is widely used in resource-constrained IoT devices due to fast and simple operation of software and hardware platforms. However, there are three weaknesses to ARX-based lightweight block ciphers. Firstly, only half of the data can be changed in one round. Secondly, traditional ARX-based lightweight block ciphers are static structures, which provide limited security. Thirdly, it has poor diffusion when the initial plaintext and key are all 0 or all 1. This paper proposes a new dynamic ARX-based lightweight block cipher to overcome these weaknesses, called DABC. DABC can change all data in one round, which overcomes the first weakness. This paper combines the key and the generalized two-dimensional cat map to construct a dynamic permutation layer P1, which improves the uncertainty between different rounds of DABC. The non-linear component of the round function alternately uses NAND gate and AND gate to increase the complexity of the attack, which overcomes the third weakness. Meanwhile, this paper proposes the round-based architecture of DABC and conducted ASIC and FPGA implementation. The hardware results show that DABC has less hardware resource and high throughput. Finally, the safety evaluation results show that DABC has a good avalanche effect and security.

• Convergence Security Journal
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• v.15 no.2
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• pp.81-89
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• 2015

HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a key scheduler that employs the presented LFSR and reverse LFSR that can generate four outputs simultaneously. In addition, we construct new key scheduler that generates 4 subkey bytes at a clock since each round block requires 4 subkey bytes at a time. Thus, the entire HIGHT processor can be controlled by single system clock with regular control mechanism. We synthesize the HIGHT processor using the VHDL. From the synthesis results, the logic size of the presented key scheduler can be reduced as 9% compared to the counterpart that is employed in the conventional HIGHT processor.

• Journal of Computational Design and Engineering
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• v.2 no.4
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• pp.206-217
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• 2015

This paper presents a complete S-shape feed rate scheduling approach (CSFA) with confined jerk, acceleration and command feed rate for parametric tool path. For a Non-Uniform Rational B-Spline (NURBS) tool path, the critical points of the tool path where the radius of curvature reaches extreme values are found firstly. Then, the NURBS curve is split into several NURBS sub-curves or blocks by the critical points. A bidirectional scanning strategy with the limitations of chord error, normal/tangential acceleration/jerk and command feed rate is employed to make the feed rate at the junctions between different NURBS blocks continuous. To improve the efficiency of the feed rate scheduling, the NURBS block is classified into three types: short block, medium block and long block. The feed rate profile corresponding to each NURBS block is generated according to the start/end feed rates and the arc length of the block and the limitations of tangential acceleration/jerk. In addition, two compensation strategies are proposed to make the feed rate more continuous and the arc increment more precise. Once the feed rate profile is determined, a second-order Taylor's expansion interpolation method is applied to generate the position commands. Finally, experiments with two free-form NURBS curves are conducted to verify the applicability and accuracy of the proposed method.

• Journal of the Korea Society of Computer and Information
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• v.13 no.4
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• pp.169-175
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• 2008

The existing block encryption algorithms have been designed for the encryption key value to be unchanged and applied to the round functions of each block. and enciphered. Therefore, it has such a weak point that the plaintext or encryption key could be easily exposed by differential cryptanalysis or linear cryptanalysis, both are the most powerful methods for decoding block encryption of a round repeating structure. Dynamic cipher has the property that the key-size, the number of round, and the plaintext-size are scalable simultaneously. Dynamic network is the unique network satisfying these characteristics among the networks for symmetric block ciphers. We analyze the strength of Dynamic network for meet-in-the-middle attack, linear cryptanalysis, and differential cryptanalysis. Also, In this paper we propose a new network called Dynamic network for symmetric block ciphers.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2333-2340
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• 2016

A LEA (Lightweight Encryption Algorithm) crypto-processor was designed, which supports three master key lengths of 128/ 192/256-bit, ECB and CTR modes of operation. To achieve high throughput rate, the round transformation block was designed with 128 bits datapath and a pipelined structure of 16 stages. Encryption/decryption is carried out through 12/14/16 pipelined stages according to the master key length, and each pipelined stage performs round transformation twice. The key scheduler block was optimized to share hardware resources that are required for encryption, decryption, and three master key lengths. The round keys generated by key scheduler are stored in 32 round key registers, and are repeatedly used in round transformation until master key is updated. The pipelined LEA processor was verified by FPGA implementation, and the estimated performance is about 8.3 Gbps at the maximum clock frequency of 130 MHz.

• Journal of the Korean Geotechnical Society
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• v.40 no.3
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• pp.101-108
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• 2024

A system with the ability to recognize potential key blocks during tunnel construction by analyzing the rock face was developed in this study. This system predicts the formation of key blocks in advance and evaluates their safety factors. A laser scanner was used to collect a three-dimensional point cloud of the rock face, which was then utilized to model the excavation surface and derive the joint surfaces. Because joint surfaces have specific strikes and dip angles, the key blocks formed by these surfaces are deduced through iterative calculations, and the safety factor of each key block can be calculated accordingly. The model experiments confirmed the accuracy of the system's output in terms of the joint surface characteristics. By inputting the joint surface information, the calculated safety factors were compared with those from the existing commercial software, demonstrating stable calculation results within a 1% error margin.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.6
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• pp.3-10
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• 2007

In this paper we present related-key differential attacks on the block-wise stream cipher TWOPRIME. We construct various related-key differentials of TWOPRIME and use them to show that recovering related keys of TWOPRIME can be performed with a data complexity of $2^{14}$ known plaintext blocks and a time complexity of $2^{38}$ 8-bit table lookups.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.165-168
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• 2000

A hardware architecture to implement the SEED block cipher algorithm into one chip is described. Each functional unit is designed with VHDL hardware description language and synthesis tools. The designed hardware receives a 128-bit block of plain text input and a 128-bit key, and generates a 128-bit cipher block after 16-round operations after 8 clocks. The encryption time is within 20 nsec.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.2
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• pp.724-737
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• 2020

Corrected Block TEA(or XXTEA) is a block cipher designed to correct security weakness in the original block TEA in 1998. In this paper, XXTEA cipher hardware which can encrypt or decrypt between 64-bit and 256-bit messages using 128-bit master key is implemented. Minimum message block size is 64-bit wide and maximal message block size is 256-bit wide. The designed XXTEA can encrypt and decrypt variable-length message blocks which are some arbitrary multiple of 32 bits in message block sizes. XXTEA core of this paper is described using Verilog-HDL and downloaded on Vertex4. The operation frequency is 177MHz. The maximum throughput for 64-bit message blocks is 174Mbps and that of 256-bit message blocks is 467Mbps. The cryptographic IP of this paper is applicable as security module of the mobile areas such as smart card, internet banking, e-commerce and IoT.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.193-202
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• 2010

This paper presents a high-speed low-complexity pipelined Reed-Solomon (RS) (255,239) decoder using pipelined reformulated inversionless Berlekamp-Massey (pRiBM) algorithm and its folded version (PF-RiBM). Also, this paper offers efficient pipelining and folding technique of the RS decoders. This architecture uses pipelined Galois-Field (GF) multipliers in the syndrome computation block, key equation solver (KES) block, Forney block, Chien search block and error correction block to enhance the clock frequency. A high-speed pipelined RS decoder based on the pRiBM algorithm and its folded version have been designed and implemented with 90-nm CMOS technology in a supply voltage of 1.1 V. The proposed RS(255,239) decoder operates at a clock frequency of 700 MHz using the pRiBM architecture and also operates at a clock frequency of 750 MHz using the PF-RiBM, respectively. The proposed architectures feature high clock frequency and low-complexity.