• Journal of Welding and Joining
• /
• v.11 no.1
• /
• pp.42-51
• /
• 1993

In this study, investigations were conducted in calculating parameters of elastic-plastic fracture mechanics using single specimen. The validity of these testing methods was judged by the confirmation of multiple specimen method of stop block test. The results were as follows: In order to measure a fracture toughness using the instrumented impact test, two general requirement must be considered; One, setting up proper impact velocity considered the effect of loading and the other, the necessity of low blow test for obtaining true energy by the compliance correction. It was possible to detect a crack initiation point by calculating the compliance changing rate from a load-defection curve. Criterion of a stable crack growth, $T_{mat}$ could be estimated by using key-curve method for a base metal. and combining Kaiser's rebound compliance with Paris-Hutchison's $T_{appl}$ equation for the brittled zone of welding heat affected.at affected.d.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
• /
• 2006.05a
• /
• pp.314-319
• /
• 2006

Main focus on balance shaft module is to reduce the vibration triggered from engine block and compensate it from unbalance mass in balance shaft. Since the performance of balance shaft module is controlled by rotor shape including unbalance mass, a design strategy on rotor is key issue on determine the quality of balance shaft system. Even the design result on balance shaft mostly affect the lay-out of housing and other related components, its issue on balance shaft should be considered in advance throughout the total design procedure. In this paper, optimal design strategy focused on balance shaft is presented to make a design process efficiently with ensuring its high performance. And its method is verified with field design process of balance shaft in commonly adapted vehicle with 3-cylinder and 4-cylinder engine.

• Journal of Electrical Engineering and information Science
• /
• v.2 no.4
• /
• pp.8-13
• /
• 1997

This paper describes a scalable systolic synchronous memory for digital signal processing and packet switching. The systolic synchronous memory consists of the 2-D array of small memory blocks which are fully pipelined and communicated in three directions with adjacent blocks. The maximum delay of a small memory block becomes the operation speed of the chip. The array configuration is scalable for the entire memory size requested by an application. it has the initial latency of N+3 cycles with NxN array configuration. We designed an experimental 200 MHz 4Kb static RAM chip with the 4x4 array configuration of 256 SRAM blocks. It was fabricated is 0.8$\mu\textrm{m}$ twin-well single-poly double-metal CMOS technology.

• Proceedings of the Korean Society of Computer Information Conference
• /
• 2018.07a
• /
• pp.445-448
• /
• 2018

본 논문에서는 데이터 이중화 저장시스템의 장애발생으로 인한 백업서버 데이터 손실을 보호하기 위해 무 손실 실시간 데이터 이중화 시스템 설계방안을 제안한다. 이는 원본서버의 데이터와 백업서버의 데이터가 특정 시점 T에서 100% 일치하지 않는 비동기 방식을 동기방식으로 해결하기 위한 시스템 설계 제안으로, 원본서버의 데이터 생성과 동시에 실시간 데이터 백업을 목적으로 한다. 이를 위해 전송단계에서 필요한 가장 빠른 압축인 LZ4 압축 알고리즘을 기반으로 Intel AVX 명령어를 사용하여 보다 압축속도를 증진시켜 실시간 시스템을 구축한다. 또한 전송 중 보안위협으로부터 보호하기 위해 Key 전달 기법과 AES 암호화 알고리즘에 대해 기술한다.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.59 no.2
• /
• pp.465-470
• /
• 2010

The charge pump in a phase-locked loop is a key block in determining reference spurs of the VCO output signal. To reduce reference spurs, the current mismatch in the charge pump must be minimized. This paper presents a dual compensation method to reduce the current mismatch. The proposed charge pump and PLL were realized in a $0.18{\mu}m$ CMOS process. Measured current matching characteristics were achieved with less than 1.4% difference and with the current variation of 3.8% in the pump current over the charge pump output voltage range of 0.35-1.35V at 1.8V. The reference spur of the PLL based on the proposed charge pump was measured to be -71dBc.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2016.05a
• /
• pp.157-159
• /
• 2016

3가지 마스터키 길이 128/192/256 비트를 지원하는 파이프라인 LEA(Lightweight Encryption Algorithm) 크립토 프로세서를 설계하였다. 높은 처리율을 얻기 위해 16개의 라운드 스테이지가 파이프라인 방식으로 동작하며, 각 라운드 스테이지는 128비트 데이터패스를 갖도록 설계하였다. 설계된 LEA 프로세서는 FPGA 구현을 통해 하드웨어 동작을 검증하였다. Xilinx ISE로 합성한 결과, 최대 동작주파수 122MHz로 동작하여 7.8Gbps의 성능을 갖는 것으로 평가되었다.

• Journal of the Korean Society for Railway
• /
• v.8 no.6 s.31
• /
• pp.559-565
• /
• 2005

In this paper, we propose a stereoscopic video coding scheme for subway accident monitoring system. The proposed designed for providing flexible video among various displays, such ass control center, station employees and train driver. We uses MPEG-2 standard for coding the left-view sequence and IBMDC coding scheme predicts matching block by interpolating both motion and disparity predicted macroblocks. To provide efficient stereoscopic video service, we define both temporally and spatially scalable layers for each eye's-view by using the concept of Spatio-Temporal scalability. The experimental results show the efficiency of proposed coding scheme by comparison with already known methods and the advantages of disparity estimation in terms of scalability overhead. According to the experimental results, we expect the proposed functionalities will play a key role in establishing highly flexible stereoscopic video codec for ubiquitous display environment where devices and network connections are heterogeneous.

• Journal of Digital Contents Society
• /
• v.8 no.4
• /
• pp.451-458
• /
• 2007

In this paper, I developed a method whereby spam mail is automatically blocked through the connection to link URL. The blocking system works as follows. First, the system extracts information of URL linked to electronic mail which was delivered from any server on the internet. Next, the system lets itself be connected to the web pages through this URL. Last, the system blocks the electronic mail if those web pages contain any key word which was defined as a clue to spam mail.

• International Journal of Railway
• /
• v.6 no.4
• /
• pp.139-147
• /
• 2013

TSR (Trans-Siberian Railway) route is losing price competitiveness versus Deep Sea route in the transportation from East Asia to Europe, including Moscow. To further attracting the containers to the TSR route, it will be necessary (1) to keep competitive through rate, linked to fluctuating Deep Sea rate; (2) to strengthen speed advantage; (3) to enforce seamless transportation system, including simplified customs clearance procedures. In transportation to Central Asia from East Asia (Korea and Japan), TSR is competitive versus TCR (Trans-China Railway), depending on destinations. Korea has been the leader in revitalizing the TSR route since 2000. Key contributors were affluent export containers to Russia and Central Asia, port of Busan, efficient maritime transport network to Far East Russia, and Korean forwarders' persistent efforts for activating the market. Korea and Japan have a possibility of cooperation in using the TSR route efficiently, such as organizing a joint block train to a same destination.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• v.9 no.2
• /
• pp.852-855
• /
• 2005

This paper introduces a case study of designing a cryptographic processor dedicated to VPN/SSL system. The designed processor supports not only block cipher algorithm, including 3DES, AES, and SEED, but also 163 bit ECC public key crypto algorithm. Moreover, we adopted PCI Master interface in the design, which guarantees fast computation of cryptographic algorithm prevalent in general information security systems.