• Journal of KIISE:Computer Systems and Theory
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• v.34 no.11
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• pp.599-609
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• 2007

Due to the restrictions of Flash memory such as overwrite limitation and write/erase operational unit differences, block cleaning is required in Flash memory based file systems and known as a key factor on the performance of file systems. In this paper, we identify three parameters, namely utilization, invalidity and uniformity, and analyze how the parameters affect the cost of block cleaning. The analysis show that as uniformity degrades, the cost of block cleaning increases drastically. To overcome this problem, we design a new modification-aware(MODA) page allocation scheme that strives to keep uniformity high by separating frequently-updating data from infrequently-updating data. Real implementation experiments conducted on an embedded system show that the MODA scheme can actually enhance uniformity of Flash memory, which consequently leads to reduce the cost of block cleaning with an average of 123%, compared to the traditional sequential allocation scheme that is used in YAFFS.

• Journal of Adhesion and Interface
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• v.9 no.4
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• pp.30-33
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• 2008

Two polymeric interfaces with single component homo-polymers were prepared to control the orientation of block copolymer thin-film nanostructures. Poly(4-acetoxy styrene) (OH-PAS) and poly(4-methoxy styrene) (OH-PMS) which have the average chemical composition of polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) were precisely synthesized through nitroxide-mediated radical polymerization. After dehydration reactions between above polymers and SiOx layers of silicon wafers, the polymer-modified interface induced partial (30%) vertical orientation of PS-b-PMMA thin film in the case of OH-PMS and wholly parallel orientation in the case of OH-PAS. Chemical compositions of polymeric interface layers are regarded as the key parameter to control the orientation of nanostructures of block copolymer thin film.

• Korean Journal of Optics and Photonics
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• v.24 no.5
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• pp.262-270
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• 2013

In this paper, we propose a modified optical CBC(Cipher Block Chaining) encryption method using optical XOR logic operations. The proposed method is optically implemented by using dual encoding and a free-space interconnected optical logic gate technique in order to process XOR operations in parallel. Also, we suggest a CBC encryption/decryption optical module which can be fabricated with simple optical architecture. The proposed method makes it possible to encrypt and decrypt vast two-dimensional data very quickly due to the fast optical parallel processing property, and provides more security strength than the conventional electronic CBC algorithm because of the longer security key with the two-dimensional array. Computer simulations show that the proposed method is very effective in CBC encryption processing and can be applied to even ECB(Electronic Code Book) mode and CFB(Cipher Feedback Block) mode.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8B
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• pp.1506-1517
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• 1999

In this paper, we propose two fast block matching algorithm using the distribution of mean absolute difference (MAD) at the search region overlapped with neighbor blocks and pixel subsapmling. The proposed methods use the lower and upper bound of MAD at the overlapped search region which is calculated from the MAD of neighbor block at that search position and MAD between the current block and neighbor block. In the first algorithm, we can reduce the computational complexity by executing the block matching operation at the only necessary search points. That points are selected using the lower bound of MAD. In the second algorithm, we use the statictical distribution of actual MAD which exists between the lower bound and upper bound of MAD. By using the statistical distribution of actual MAD, we can significantly reduce the computational complexity for motion estimation. after striking space key 2 times.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.6A
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• pp.51-61
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• 2008

This paper suggests a new way to implement high speed AES on Intel Core2 processors and AMD Athlon64 processors, which are used all over the world today. First, Core2 Processors of EM64T architecture's memory-access-instruction processing efficiency are lower than calculus-instruction processing efficiency. So, previous AES implementation techniques, which had a high rate of memory-access-instruction, could cause memory-bottleneck. To improve this problem we present the partial round key techniques that reduce the rate of memory-access-instruction. The result in Intel Core2Duo 3.0 Ghz Processors show 185 cycles/block and 2.0 Gbps's throughputs in ECB mode. This is 35 cycles/block faster than bernstein software, which is known for being the fastest way. On the other side, in AMD64 processors of AMD64 architecture, by removing bottlenecks that occur in decoding processing we could improve the speed, with the result that the Athlon64 processor reached 170 cycles/block. The result that we present is the same performance of Matsui's unpublished software.

• ETRI Journal
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• v.32 no.6
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• pp.972-975
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• 2010

In this letter, we consider the lossy coding of a non-uniform binary source based on GF(q)-quantized low-density generator matrix (LDGM) codes with check degree $d_c$=2. By quantizing the GF(q) LDGM codeword, a non-uniform binary codeword can be obtained, which is suitable for direct quantization of the non-uniform binary source. Encoding is performed by reinforced belief propagation, a variant of belief propagation. Simulation results show that the performance of our method is quite close to the theoretic rate-distortion bounds. For example, when the GF(16)-LDGM code with a rate of 0.4 and block-length of 1,500 is used to compress the non-uniform binary source with probability of 1 being 0.23, the distortion is 0.091, which is very close to the optimal theoretical value of 0.074.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.164-167
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• 2002

This paper presents the design of Rijndael crypto-processor with 128 bits, 192 bits and 256 bits key size. In October 2000 Rijndael cryptographic algorithm is selected as AES(Advanced Encryption Standard) by NIST(National Institute of Standards and Technology). Rijndael algorithm is strong in any known attacks. And it can be efficiently implemented in both hardware and software. We implement Rijndael algorithm in hardware, because hardware implementation gives more fast encryptioN/decryption speed and more physically secure. We implemented Rijndael algorithm for 128 bits, 192 bits and 256 bits key size with VHDL, synthesized with Synopsys, and simulated with ModelSim. This crypto-processor is implemented using on-the-fly key generation method and using lookup table for S-box/SI-box. And the order of Inverse Shift Row operation and Inverse Substitution operation is exchanged in decryption round operation of Rijndael algorithm. It brings about decrease of the total gate count. Crypto-processor implemented in these methods is applied to mobile systems and smart cards, because it has moderate gate count and high speed.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.5
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• pp.2317-2321
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• 2011

This paper is proposed new data crytoblock algorithm based on the private key cryptoalgorithim with existed other cryptography algorithims. Therefore new crytoblock design and simulation using the common Synopsys and ALTERA Max+ PlusII Ver.10.1. As a simulation result, new data crytoblock have gate counting 640Mbps at the 40M hz. We thought that proposed new data crytoblock adapt real time information security.

• Journal of information and communication convergence engineering
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• v.15 no.3
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• pp.160-164
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• 2017

Public key cryptography (PKC) is the basic building block for the cryptography applications such as encryption, key distribution, and digital signature scheme. Among many PKC, elliptic curve cryptography (ECC) is the most widely used in IT systems. Recently, very efficient Montgomery-Twisted-Edward (MoTE)-ECC was suggested, which supports low complexity for the finite field arithmetic, group operation, and scalar multiplication. However, we cannot directly adopt the MoTE-ECC to new PKC systems since the cryptography is not fully evaluated in terms of performance on the Internet of Things (IoT) platforms, which only supports very limited computation power, energy, and storage. In this paper, we fully evaluate the MoTE-ECC implementations on the representative IoT devices (16-bit MSP processors). The implementation is highly optimized for the target platform and compared in three different factors (ROM, RAM, and execution time). The work provides good reference results for a gradual transition from legacy ECC to MoTE-ECC on emerging IoT platforms.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.341-344
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• 2002

The importance of protection for information is increasing by the rapid development of information communication and network. Asymmetric crypto-system is the mainstream in encryption system rather than symmetric cryptosystem by above reasons. But asymmetric cryptosystem is restricted in applying to application fields by the reason it takes more times to process than symmetric cryptosystem. In this paper, the proposed cryptosystem uses an algorithm that combines block cipherment with stream ciphcrment. Proposed cryptosystem has a high stability in aspect of secret rate by means of transition of key sequence according to the information of plaintext while asymmetric /symmetric cryptosystern conducts encipherment/decipherment using a fixed key Consequently, it is very difficult to crack although unauthenticator acquires the key information. So, the proposed encryption system which has a certification function of asymmetric cryptosystcm and a processing time equivalent to symmetric cryptosystcm will be highly useful to authorize data or exchange important information.