• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.3
• /
• pp.411-424
• /
• 2017

An all-digital delay-locked loop (DLL) for a mobile memory interface, which runs at 0.11-2.5 GHz with a phase-shift capability of $180^{\circ}$, has two internal DLLs: a global DLL which uses a time-to-digital converter to assist fast locking, and shuts down after locking to save power; and a local DLL which uses a phase detector with an adaptive phase sampling window (WPD) to reduce jitter accumulation. The WPD in the local DLL adjusts the width of its sampling window adaptively to control the loop bandwidth, thus reducing jitter induced by UP/DN dithering, input clock jitter, and supply/ground noise. Implemented in a 65 nm CMOS process, the DLL operates over 0.11-2.5 GHz. It locks within 6 clock cycles at 0.11 GHz, and within 17 clock cycles at 2.5 GHz. At 2.5 GHz, the integrated jitter is $954fs_{rms}$, and the long-term jitter is $2.33ps_{rms}/23.10ps_{pp}$. The ratio of the RMS jitter at the output to that at the input is about 1.17 at 2.5 GHz, when the sampling window of the WPD is being adjusted adaptively. The DLL consumes 1.77 mW/GHz and occupies $0.075mm^2$.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.24 no.4
• /
• pp.548-552
• /
• 1987

The constraint condition of the loop filter is persented for the convergence of the random jitter accumulation fo the 2-nd order PLL (phase-locked loop) circuit used in digital regenerative repeater. This condition is confirmed under the assumption that the number of repeater chain is 5, bandwidth is 100. 0KHz, the power spectral density of white Gaussian noise is 1.0x10**-6 [W/Hz]. Also, it is shown that if the condition is satisfied, the accumulated random jitter and the alignment jitter will have the saturation characteristics.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2003.10a
• /
• pp.394-397
• /
• 2003

Since the speed of operation in the system has been increasing rapidly, chips should have been synchronized. Then, synchronized circuits such as PLL (Phase Locked Loop), DLL (Delay Locked Loop) are used. VCO (Voltage Controled Oscillator) generated a frequency in the PLL has disadvantage such as jitter accumulation. On the other hands, VCDL (Voltage Controled Delay Line) used at DLL has an advantage which has no jitter accumulation. In this paper, a new and improved VCDL structure is suggested.

• Korean Journal of Optics and Photonics
• /
• v.14 no.3
• /
• pp.215-218
• /
• 2003

A 2R O/E/O wavelength converter is useful for bit rate transparency, though it has a limit on cascadability due to timing-jitter accumulation. In this paper, we propose a nonlinear signal model which is more practical than the commonly used sine wave model. With our model, we theoretically analyzed the effects of timing-jitter and the cascadability of a 2R O/E/O wavelength converter. To confirm the theoretical results, we measured the cascadability in a 40-km re-circulation loop for 10 Gb/s signal.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.19 no.8
• /
• pp.1558-1570
• /
• 1994

The ideal stuffing jitter in a chain of stuffing systems is analyzed. The great jitter is generated when stuffing system operates with a stuffing ratio close to a simple rational number. The rms amplitude and probability density function of the accumulated jitter on the output of the chain is calculated and experimentally analyzed with a help of a hardware stuffing simulator.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.1A
• /
• pp.83-90
• /
• 2007

In this paper, we propose an implementation and an algorithm of 'Jitter and Glitch Removing Circuit' for UHF RFID reader system based on ISO/IEC 18000-6C standard. We analyze the response of TI(Texas Instrument) Gen2 tag with a reader using the proposed algorithm. In ISO/IEC 18000-6C standard, a bit rate accuracy(tolerance) is up to +/-22% during tag-to-interrogator communication and +/-1% during interrogator-to-tag communication. In order to solve tolerance problems, we implement the Jitter and Glitch Removing Circuit using the concept of tolerance and tolerance-accumulation instead of PLL(DPLL, ADPLL). The main clock is 19.2MHz and the LF(Link Frequency) is determined as 40kHz to meet the local radio regulation in korea. As a result of simulations, the error-rate is zero within 15% tolerance of tag responses. And in the case of using the adaptive LF generation circuit, the error-rate varies from 0.000589 to zero between 15% and 22% tolerance of tag responses. In conclusion, the error-rate is zero between 0%-22% tolerance of tag response specified in ISO/IEC 18000-6C standard.

• The Journal of the Acoustical Society of Korea
• /
• v.5 no.2
• /
• pp.13-18
• /
• 1986

디지틀 데이터 전송시 수신기에서 또는 중계기에서 송신 데이터를 구하기 위해서는 타이밍 클럭 을 복원해야 한다. 대개의 실장된 경우에서는 PLL을 이용하는데, 이때 시스템/랜덤 지터가 발생되고 또 중계기가 늘어남에 따라서 생성된 지터가 누적되는데 이것을 해석하였다. 90 Mbps 광통신 시스템에 적 용하여 테이블 1,2,3,4와 같은 결과를 얻었으며, 시스템 지터가 랜덤 지터보다 더 급격히 누적됨을 알았 고, 또한 댐핑팩터가 커짐에 따라 지터 누적이 양화됨을 알았다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.37 no.5C
• /
• pp.420-428
• /
• 2012

One of the most important means in modern NQ emphasized smart society is the communication skill. Especially, effects on improving pronunciation accuracy, it is mostly necessary to accurately express his or her own idea due to the personal relation influence 38% of voice. For this, this paper proposed the voice influence analysis of carbonate drink and eucalyptus fragrance. In particular, in the case of carbonate drink, the amounts of drinking accumulation is verified for analysing the drinking accumulation influence. Also, eucalyptus fragrance is reported for influencing the pronunciation accuracy. For this, jitter, shimmer, pitch and intensity of voice is analyzed. Finally, we accomplish an voice analysis of quantization, objective and visualization for such carbonate drink and eucalyptus fragrance.