• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.86-89
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• 1994

This paper describes the fabrication and basic characteristics of a Si Hall device fabricated on a SOI(Si-on-insulator) structure. In which SOI structure was formed by SOB(Si-wafer direct bonding) technology and the insulator of the SOI structure was used as the dielectrical isolation layer of a Hall device. The Hall voltage and sensitivity of the implemented SDB SOI Hall devices showed good linearity with respectivity to the applied magnetic flux density and supple iud current. The product sensitivity of the SDB SOI Hall device was average 670 V/A$.$T and its value has been increased up to 3 times compared to that of bulk Si with buried layer of 10$\mu\textrm{m}$. Moreover, this device can be used at high-temperature, high-radiation and in corrosive environments.

• Proceedings of the Optical Society of Korea Conference
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• 2004.02a
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• pp.298-299
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• 2004

We propose and theoretically analyze multi-functional integrated optical device based on figure-eight shaped birefringent Sagnac loops. Our analysis shows that the propose device exhibit many unique features which allows it to operate as a tunable high-Q comb filter with a good channel isolation, and the intensity transmission of the filter can be varied from zero to 100 percent.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.5
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• pp.370-374
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• 1991

A high performance fully ion-implanted InP JFET was characterized for high speed switching elements. The switch has an insertion loss of 5.5dB with 31.6dB isolation at 1GHz. This device can effectively swithc a byte-multiplexed 2Gb/s signal and an eye-diagram taken at 2Gb/s shows an error-free eye pattern. Therefore, this device can be used as a switching element for high transmission data rate for monolithic integration of optoelectronic circuit in the long-wavelength region.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2002.10b
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• pp.443-444
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• 2002

The uniformity of field oxide is critical to isolation property of device in STI, so the control of field oxide thickness in STI-CMP becomes enormously important. The loss of field oxide in shallow trench isolation comes mainly from dishing and erosion in STI-CMP. In this paper, the effect of slurries on the dishing was investigated with both blanket and patterned wafers were selected to measure the removal rate, selectivity and dishing amount. Dishing was a strong function of pattern spacing and types of slurries. Dishing was significantly decreased with decreasing pattern spacing for both slurries. Significantly lower dishing with ceria based slurry than with silica based slurry were achieved when narrow pattern spacing were used. Possible dishing mechanism with two different slurries were discussed based on the observed experimental results.

• Proceedings of the Earthquake Engineering Society of Korea Conference
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• 2002.03a
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• pp.383-390
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• 2002

The new seismic isolation system (StLRB) is developed, which can separate non-seismic displacements which come from the thermal expansion etc. in LRB design. The StLRB has 3 components, sliding system (PTFE + stainless plate), LRB (lead rubber bearing) and STU (shock transmit units). In this project, the StLRB is designed to apply to the bridge structure by analyzing the characteristics of each component and also the dynamic behavior of the structure was analyzed by non-linear analysis. The verification test was performed to show the two stages separated by STU units. Test results show the effectiveness of both the separation and the seismic isolation performance.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2002.05a
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• pp.272-278
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• 2002

Recently, STI(Shallow Trench Isolation) process has attracted attention for high density of semiconductor device as a essential isolation technology. In this paper, the effect of pattern density, trench width and selectivity of slurry on dishing in STI CMP process was investigated by using specially designed isolation pattern. As trench width increased, the dishing tends to increase. At $20{\mu}m$ pattern size, the dishing was decreased with increasing pattern density Low selectivity slurry shows less dishing at over $160{\mu}m$ trench width, whereas high selectivity slurry shows less dishing at below $160{\mu}m$ trench width.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.25-28
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• 2001

Recently, STI(Shallow Trench Isolation) process has attracted attention for high density of semiconductor device as a essential isolation technology. Without applying the conventional complex reverse moat process, CMP(Chemical Mechanical Polishing) has established the Process simplification. However, STI-CMP process have various defects such as nitride residue, torn oxide defect, damage of silicon active region, etc. To solve this problem, in this paper, we discussed to determine the control limit of process, which can entirely remove oxide on nitride from the moat area of high density as reducing the damage of moat area and minimizing dishing effect in the large field area. We, also, evaluated the reliability and reproducibility of STI-CMP process through the optimal process conditions.

• The Magazine of the IEIE
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• v.24 no.6
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• pp.38-49
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• 1997

0.4mm Resign Rule의 Super Low Power Dissipation, Low Voltage. Operation-5- Full CMOS SRAM Cell을 개발하였다. Retrograde Well과 PSL(Poly Spacer LOCOS) Isolation 공정을 사용하여 1.76mm의 n+/p+ Isolation을 구현하였으며 Ti/TiN Local Interconnection을 사용하여 Polycide수준의 Rs와 작은 Contact저항을 확보하였다. p-well내의 Boron이 Field oxide에 침적되어 n+/n-well Isolation이 취약해짐을 Simulation을 통해 확인할 수 있었으며, 기생 Lateral NPN Bipolar Transistor의 Latch Up 특성이 취약해 지는 n+/n-wellslze는 0.57mm이고, 기생 Vertical PNP Bipolar Transistor는 p+/p-well size 0.52mm까지 안정적인 Current Gain을 유지함을 알 수 있었다. Ti/TiN Local Interconnection의 Rs를 Polycide 수준으로 낮추는 것은 TiN deco시 Power를 증가시키고 Pressure를 감소시킴으로써 실현할 수 있었다. Static Noise Margin분석을 통해 Vcc 0.6V에서도 Cell의 동작 Margin이 있음을 확인할 수 있었으며, Load Device의 큰 전류로 Soft Error를 개선할수 있었다. 본 공정으로 제조한 1M Full CMOS SRAM에서 Low Vcc margin 1.0V, Stand-by current 1mA이하(Vcc=3.7V, 85℃기준) 를 얻을 수 있었다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.1
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• pp.110-116
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• 2012

This paper proposes a new diversity antenna which is the base of MIMO, tunable and reconfigurable antennas. The antenna has a small size and high inter-antenna isolation resulting from the compact radiating element comprising a meandered line and an open-loop combined in one limited uniplanar space and a modified T-shaped decoupling structure, respectively. In a WiMAX band, the radiating element and the entire antenna are $0.092{\lambda}$ and $0.2216{\lambda}$ in size, which shows effective size-reduction and the gain and efficiency of the proposed antenna attached to the ground of a handheld device are 3.7dBi and 56% acceptable to the industrial standard.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.801-806
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• 1986

The effect of SiH2Cl2 -HCl gas on the growth rate of epitaxial layer is studied. The temperature, pressure and gas mixing ratio of SiH2Cl2 and HCl are varied to study the growth rate dependence and selective Si epitaxy. The P-n junction diode is fabricated on the epitaxial layer and electrical characteristics are examined. Also, using selective Si epitaxy, a possibility of thin dielectric isolation process, that gives an independent isolation width on the mask dimension, is examined.