• Journal of the Korean Vacuum Society
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• v.16 no.3
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• pp.210-214
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• 2007

We have studied optical transitions of Gd-implanted GaN epilayers. Photoluminescence transition intensity at 590 nm at T=5 K diminishes and its center position moves to short avelength (blue shift) with increasing temperature up to 200 K. Above T=200 K, the transition intensity increases with increasing temperature while the center position remains the same. We believe that such anomalous optical transition behavior is due to the effect of rare-element in the semiconductor host material and lattice imperfection which was occurred during the implantation process well as.

• Journal of the Korean Vacuum Society
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• v.14 no.2
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• pp.91-96
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• 2005

The silicon-on-insulator (SOI) wafer fabrication technique has been developed by using ion-cut process, based on proton implantation and wafer bonding techniques. It has been shown by SRIM simulation that 65keV proton implantation is required for a SOI wafer (200nm SOI, 400nm BOX) fabrication. In order to investigate the optimum proton dose and primary annealing condition for wafer splitting, the surface morphologic change has been observed such as blistering and flaking. As a result, effective dose is found to be in the $6\~9\times10^{16}\;H^+/cm^2$ range, and the annealing at $550^{\circ}C$ for 30 minutes is expected to be optimum for wafer splitting. Direct wafer bonding is performed by joining two wafers together after creating hydrophilic surfaces by a modified RCA cleaning, and IR inspection is followed to ensure a void free bonding. The wafer splitting was accomplished by annealing at the predetermined optimum condition, and high temperature annealing was then performed at $1,100^{\circ}C$ for 60 minutes to stabilize the bonding interface. TEM observation revealed no detectable defect at the SOI structure, and the interface trap charge density at the upper interface of the BOX was measured to be low enough to keep 'thermal' quality.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.108-116
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• 1996

A semiconductor process imulator operated in windows$^{TM}$ environment has been developed. two-dimensional process simulation in personal computer has been enabled due to the improvement of CPU speed and the efficient use of memory. The process simulator in this paper is capable of calculating diffusion, oxidation, ion implantation, etching and deposition in two-dimensional manner. In addition, graphic-user-friendly editor, parser, and multi-dimensional graphical routine is also available in the devloped simulator.

• Journal of the Korean Vacuum Society
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• v.11 no.3
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• pp.151-158
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• 2002

Fabricated were ultra-shallow $p^+-n$ junctions on n-type Si(100) substrates using decaborane $(B_{10}H_{14})$ ion implantation. Decaborane ions were implanted at the acceleration voltages of 5 kV to 10 kV and at the dosages of $1\times10^{12}\textrm{cm}^2$.The implanted specimens were annealed at $800^{\circ}C$, $900^{\circ}C$ and $1000^{\circ}C$ for 10 s in $N_2$ atmosphere through a rapid thermal process. From the measurement of the implantation-induced damages through $2MeV^4 He^{2+}$ channeling spectra, the implanted specimen at the acceleration voltage of 15 kV showed higher backscattering yield than those of the bare n-type Si wafer and the implanted specimens at 5 kV and 10 kV. From the channeling spectra, the calculated thicknesses of amorphous layers induced by the ioin implantation at the acceleration voltages of 5 kV, 10 kV and 15 kV were 1.9 nm, 2.5 nm and 4.3 nm, respectively. After annealing at $800^{\circ}C$ for 10 s in $N_2$ atmosphere, most implantation-induced damages of the specimens implanted at the acceleration voltage of 10 kV were recovered and they exhibited the same channeling yield as the bare Si wafer. In this case, the calculated thickness of the amorphous layer was 0.98 nm. Hall measurements and sheet resistance measurements showed that the dopant activation increased with implantation energy, ion dosage and annealing temperature. From the current-voltage measurement, it is observed that leakage current density is decreased with the increase of annealing temperature and implantation energy.

• Electrical & Electronic Materials
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• v.8 no.6
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• pp.708-714
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• 1995

We have discussed the buried-channel(BC) behavior through the subthreshold characteristics of submicron PMOSFET device fabricated with twin well CMOS process. In this paper, we have guessed the initial conditions of ion implantation using process simulation, obtained the subthreshold characteristics as a function of process parameter variation such as threshold adjusting ion implant dose($D_c$), channel length(L), gate oxide thickness($T_ox$) and junction depth of source/drain($X_j$) using device simulation. The buried channel behavior with these process prarameter variation were showed apparent difference. Also, the fabricated pMOSFET device having different channel length represented good S.S value and low leakage current with increasing drain voltage.

• Korean Journal of Materials Research
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• v.13 no.1
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• pp.43-47
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• 2003

As and BF$_2$dopants are implanted for the formation of source/drain with dose of 1${\times}$10$^{15}$ ions/$\textrm{cm}^2$∼5${\times}$10$^{15}$ ions/$\textrm{cm}^2$ then formed cobalt disilicide with Co/Ti deposition and doubly rapid thermal annealing. Appropriate ion implantation and cobalt salicide process are employed to meet the sub-0.13 $\mu\textrm{m}$ CMOS devices. We investigated the process results of sheet resistance, dopant redistribution, and surface-interface microstructure with a four-point probe, a secondary ion mass spectroscope(SIMS), a scanning probe microscope (SPM), and a cross sectional transmission electron microscope(TEM), respectively. Sheet resistance increased to 8%∼12% as dose increased in $CoSi_2$$n^{＋}$ and $CoSi_2$$p^{V}$ , while sheet resistance uniformity showed very little variation. SIMS depth profiling revealed that the diffusion of As and B was enhanced as dose increased in $CoSi_2$$n^{＋}$ and $CoSi_2$$p^{＋}$ . The surface roughness of root mean square(RMS) values measured by a SPM decreased as dose increased in $CoSi_2$$n^{＋}$ , while little variation was observed in $CoSi_2$$p^{＋}$ . Cross sectional TEM images showed that the spikes of 30 nm∼50 nm-depth were formed at the interfaces of $CoSi_2$$n^{＋}$ / and $CoSi_2$/$p^{＋}$, which indicate the possible leakage current source. Our result implied that Co/Ti cobalt salicide was compatible with high dose sub-0.13$\mu\textrm{m}$ process.

• Journal of the Korean Society of Safety
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• v.20 no.1 s.69
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• pp.18-23
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• 2005

This study deals with the friction and wear characteristics of C-N coated SCM415 steel. The PSII(plasma source ion implantation) apparatus was built and a SCM415 test piece with steel substrate was treated with carbon nitrogen by this apparatus. The composition and structure of the surface layer were analyzed and compared with that of PVD(physical vapor decomposition) coated TiN layer. It was found that both of friction coefficient of C-N coating and TiN coating decreased with increasing load, however, C-N coating showed relatively lower faction coefficient than that of TiN coating. The micro-vickers hardness of C-N film is 3200 Hv, which is $32\~43\%$ higher than that of TiN film. The critical load of C-N film is 52N, which is $25\%$ higher than that of TiN film. The hardness of C-N film fabricated by Plasma ion implantation is $61\~70\%$ higher than that of base material, and faction coefficient is $14\~50\%$ lower than that of base material. It is also interesting to note that the friction was changed from adhesive wear mode to light oxidizing wear mode.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2007.06a
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• pp.109-112
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• 2007

In this paper we describe a robust method of improving precision in monitoring high energy ion implantation processes. Ion implant energy accuracy was measured in the device manufacturing process using an unpatterned implanted layer on an intrinsic p-type silicon wafer. To increase Rs sensitivity to energy at the well implant process, a PN junction structure was formed by P-well and deep N-well implants into the p-type Si wafer. It was observed that the depletion layer formed by the PN junction was very sensitive to energy variation of the well implant. Conclusively, it can be recommended to monitor well implant processes using the Rs measurement method described herein, i.e., a PN junction diode structure since it shows excellent Rs sensitivity to variation caused by energy difference at the well implant step.

• Journal of IKEEE
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• v.27 no.4
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• pp.556-560
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• 2023

In this study, the impact of Nitrogen implantation process on deep-level defects and lifetime in 4H-SiC Epi surfaces was comparatively analyzed. Deep Level Transient Spectroscopy (DLTS) and Time Resolved Photoluminescence (TR-PL) were employed to measure deep-level defects and carrier lifetime. As-grown Schottky Barrier Diodes (SBDs) exhibited energy levels at 0.16 eV, 0.67 eV, and 1.54 eV, while for implantation SBD, defects at 0.15 eV were observed. This indicates a reduction in defects associated with energy levels Z_1/2 and EH_6/7, known as lifetime killers, as impurities from nitrogen implantation replace titanium and carbon vacancies.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.290-293
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• 2003

Ohmic contact characteristics of Al ion implanted n-type SiC wafer were investigated. Al ions implanted with high dose to obtain the final concentration of $5{\times}10^{19}/cm^3$, then annealed at high temperature. Firstly, B ion ion implanted p-well region were formed which is needed for fabrication of SiC devices such as DIMOSFET and un diode. Secondly, Al implanted high dose region for ohmic contact were formed. After ion implantation, the samples were annealed at high temperature up to $1600^{\circ}C\;and\;1700^{\circ}C$ for 30 min in order to activate the implanted ions electrically. Both the inear TLM and circular TLM method were used for characterization. Ni/Ti metal layer was used for contact metal which is widely used in fabrication of ohmic contacts for n-type SiC. The metal layer was deposited by using RF sputtering and rapid thermal annealed at $950^{\circ}C$ for 90sec. Good ohmic contact characteristics could be obtained regardless of measuring methods. The measured specific contact resistivity for the samples annealed at $1600^{\circ}C\;and\;1700^{\circ}C$ were $1.8{\times}10^{-3}{\Omega}cm^2$, $5.6{\times}10^{-5}{\Omega}cm^2$, respectively. Using the same metal and same process of the ohmic contacts in n-type SiC, it is found possible to make a good ohmic contacts to p-type SiC. It is very helpful for fabricating a integrated SiC devices. In addition, we obtained that the ratio of the electrically activated ions to the implanted Al ions were 10% and 60% for the samples annealed at $1600^{\circ}C\;and\;1700^{\circ}C$, respectively.