• Journal of Korean Vacuum Science & Technology
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• v.6 no.2
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• pp.62-66
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• 2002

Hydraulic pumps are used to control the landing wheels of aircrafts, and their proper operation is vital to plane safety It is well hewn that adhesive wear failure is a major cause of pump failure. A dual nitrogen plasma immersion ion implantation process calling for the implantation of nitrogen at two different energies and doses has been developed to enhance the surface properties of the disks in the pumps. The procedures meet the strict temperature requirement of <200$^{\circ}C$, and after the treatment, the working lifetime of the pumps increases by more than a factor of two. This experimental protocol has been adopted by the hydraulic pump factory as a standard manufacturing procedure.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1553-1555
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• 1996

This paper deals with latchup effect in CMOS retrograde well, focusing on their dependence on I/I energy conditions, so we derived some latchup characteristics from simulation for different I/I conditions on implantation energies which were used in process simulation. From these results, we could understand the dependency of CMOS retrograde well latchup on I/I energy condition.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.6
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• pp.969-974
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• 1987

High value sheet resistance (Rs, 350 \ulcorner/ -80 K \ulcorner/ ) borom implanted polysilicon resistors were fabricated under process condition compatible with bipolar integrated circuits fabrication. This paper includes the effect of contact ion implantation on Rs and the effect of electron gun(e-gun) deosition vs. non e-gun evaporated metal contacts on the Rs. From results, we observed that the contact ion implanted samples showed higher Rs value than those without contact ion implantation. Also, it was shown that there is noticeable amount of Rs degradation for e-gun samples, while sputtered samples expressed little Rs degradation after PtSi was formed.

• Transactions on Electrical and Electronic Materials
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• v.12 no.1
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• pp.16-19
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• 2011

The oxide-nitride-oxide (ONO) deposition process was added to the beginning of a 0.25 ${\mu}m$ embedded polysiliconoxide-nitride-oxide-silicon (SONOS) process before all of the logic well implantation processes in order to maintain the characteristics of basic CMOS(complementary metal-oxide semiconductor) logic technology. The system subsequently suffered severe ONO rupture failure. The damage was caused by the ONO implantation and was responsible for the ONO rupture failure in the embedded SONOS process. Furthermore, based on the experimental results as well as an implanted ion's energy loss model, processes primarily producing permanent displacement damages responsible for the ONO rupture failure were investigated for the embedded SONOS process.

• Journal of the Korean Vacuum Society
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• v.4 no.S2
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• pp.115-130
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• 1995

In order to produce Cu nanocrystallite in silicon wafer, the implantation technique was used. The samples of silicon (100) wafers were implanted by $Cu^+$ ions at 100 keV and with varying the doses at room temperature. Post-annealing was performed at $800^{\circ}C$ with Ar environment. To investigate the formation of Cu nanocrystallite with ion doses and growth process by thermal annealing, SIMS and HRTEM(high resolution transmission electron microscopy)spectra were studied.

• Clean Technology
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• v.29 no.4
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• pp.255-261
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• 2023

Power semiconductors are semiconductors used for power conversion, transformation, distribution, and control. Recently, the global demand for high-voltage power semiconductors is increasing across various industrial fields, and optimization research on high-voltage IGBT components is urgently needed in these industries. For high-voltage IGBT development, setting the resistance value of the wafer and optimizing key unit processes are major variables in the electrical characteristics of the finished chip. Furthermore, the securing process and optimization of the technology to support high breakdown voltage is also important. Etching is a process of transferring the pattern of the mask circuit in the photolithography process to the wafer and removing unnecessary parts at the bottom of the photoresist film. Ion implantation is a process of injecting impurities along with thermal diffusion technology into the wafer substrate during the semiconductor manufacturing process. This process helps achieve a certain conductivity. In this study, dry etching and wet etching were controlled during field ring etching, which is an important process for forming a ring structure that supports the 3.3 kV breakdown voltage of IGBT, in order to analyze four conditions and form a stable body junction depth to secure the breakdown voltage. The field ring ion implantation process was optimized based on the TEG design by dividing it into four conditions. The wet etching 1-step method was advantageous in terms of process and work efficiency, and the ring pattern ion implantation conditions showed a doping concentration of 9.0E13 and an energy of 120 keV. The p-ion implantation conditions were optimized at a doping concentration of 6.5E13 and an energy of 80 keV, and the p+ ion implantation conditions were optimized at a doping concentration of 3.0E15 and an energy of 160 keV.

• Proceeding of EDISON Challenge
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• 2016.03a
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• pp.344-346
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• 2016

본 논문에서는 3-stream model에 기반한 Dopant diffusion simulator를 사용하여 실리콘 기판 내부의 As이온의 확산을 시뮬레이션한 결과와 Dual-Pearson Analytic model에 기반하여 Ion implantation을 1-D doping simulation한 결과를 토대로 여러 공정 설계에서 diffusion simulator의 사용가능함을 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.23-31
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• 2008

Experiment results are presented for gate oxide degradation under the constant voltage stress conditions using MOSFETs with 3-nm-thick gate oxides that are treated by deuterium gas. Two kinds of methods, annealing and implantation, are suggested for the effective deuterium incorporation. Annealing process was rather difficult to control the concentration of deuterium. Because the excess deuterium in gate oxide could be a precursor for the wear-out of gate oxide film, we found annealing process did not show improved characteristics in device reliability, compared to conventional process. However, deuterium implantation at the back-end process was effective method for the deuterated gate oxide. Device parameter variations as well as the gate leakage current depend on the deuterium concentration and are improved by low-energy deuterium implantation, compared to those of conventional process. Especially, we found that PMOSFET experienced the high voltage stress shows a giant isotope effect. This is likely because the reaction between "hot" hole and deuterium is involved in the generation of oxide trap.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.266-269
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• 2000

As the device geometry continuously shrink down less than sub-quarter micrometer, DRAM makers are going to replace conventional tungsten-polycide with tungsten bit-line structure in order to reduce the chip size and use it as a local interconnection. In this paper we showed low resistance and leakage tungsten bit-line process with various RTP(Rapid Thermal Process) temperature. As a result we obtained that major parameters impact on tungsten bit-line process are RTP Anneal temperature and BF2 ion implantation dopant. These tungsten bit-line process are promising to fabricate high density chip technology.

• Proceedings of the Korean Vacuum Society Conference
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• 1997.02a
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• pp.98-99
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• 1997