• 한국진공학회지
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• 제22권1호
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• pp.31-36
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• 2013

마이크로플라즈마 화학기상증착법(microwave plasma enhanced chemical vapor deposition, MPCVD)에 의하여 형성된 비정질 탄소 박막의 효율적인 도핑 공정을 위하여, 비정질 탄소 박막의 성장 직전 nucleated seed 상태의 기판 혹은 일부 성장된 박막 위에 비소(As) 이온을 이온 주입하였고 그 직후 다시 MPCVD에 의하여 박막을 성장시켰다. MPCVD에 의한 성장 자체가 약 $500{\sim}600^{\circ}C$ 온도에서의 어닐링 공정을 대체할 수 있으므로, 기존의 이온 주입 후 별도의 어닐링 공정과 비교 시 간략화된 공정으로도 어닐링 효과가 있다고 할 수 있다. 이온 주입 후 박막 성장으로 어닐링 효과를 얻은 비정질 탄소 박막의 경우, $2.5V/{\mu}m$의 전계에서 약 $0.1mA/cm^2$의 전계 방출 특성을 관찰할 수 있었고 또한 라만 스펙트럼 특성에서도 다이아몬드 특성 및 그래파이트 특성 모두 뚜렷이 관찰되었다. 전기적, 구조적 특성 관찰로부터 이온 주입된 As 이온이 자동 어닐링 효과에 의해 충분히 비정질 탄소 박막에 도핑되었다고 할 수 있다.

• 전자공학회논문지D
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• 제35D권6호
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• pp.37-45
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• 1998

본 논문에서는 본 연구진이 개발 중인 INPROS 3차원 반도체 공정 시뮬레이터 시스템에 이온주입된 불순물의 과도 확산(TED, transient enhanced diffusion) 기능을 첨가하여 수행한 계산 결과를 발표한다. 실리콘 내부에 이온주입된 불순물의 재분포를 시뮬레이션하기 위하여, 먼저 몬테카를로 방법으로 이온주입 공정을 수행하였고, 유한요소법을 이용하여 확산 공정을 수행하였다. 저온 열처리 공정에서의 붕소의 과도 확산을 확인하기 위하여, 에피 성장된 붕소 에피층에 비소와 인을 이온 주입시킨 후, 750℃의 저온에서 2시간 동안 열처리 공정을 수행하였다. 3차원 INPROS 시뮬레이터의 결과와 실험적으로 측정한 SIMS 데이터와 그 결과가 일치함을 확인하였다. INPROS의 점결함 의존성 과도 증속 확산 모델과 소자 시뮬레이터인 PISCES를 이용하여 역 단채널 길이 효과(RSCE, reverse short channel effect)를 시뮬레이션하였다.

• 한국재료학회지
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• 제18권10호
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• pp.552-556
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• 2008

Modified thermal annealing was applied to the activation of the polycrystalline silicon films doped as p-type through implantation of $B_2H_6$. The statistical design of experiments was successfully employed to investigate the effect of rapid thermal annealing on activation of polycrystalline Si doped as p-type. In this design, the input variables are furnace temperature, power of halogen lamps, and alternating magnetic field. The degree of ion activation was evaluated as a function of processing variables, using Hall effect measurements and Raman spectroscopy. The main effects were estimated to be furnace temperature and RTA power in increasing conductivity, explained by recrystallization of doped ions and change of an amorphous Si into a crystalline Si lattice. The ion activation using rapid thermal annealing is proven to be a highly efficient process in low temperature polycrystalline Si technology.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권3호
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• pp.196-208
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• 2007

An analytical model is proposed for an optically controlled Metal Semiconductor Field Effect Transistor (MESFET), known as Optical Field Effect Transistor (OPFET) considering the diffusion fabrication process. The electrical parameters such as threshold voltage, drain-source current, gate capacitances and switching response have been determined for the dark and various illuminated conditions. The Photovoltaic effect due to photogenerated carriers under illumination is shown to modulate the channel cross-section, which in turn significantly changes the threshold voltage, drainsource current, the gate capacitances and the device switching speed. The threshold voltage $V_T$ is reduced under optical illumination condition, which leads the device to change the device property from enhancement mode to depletion mode depending on photon impurity flux density. The resulting I-V characteristics show that the drain-source current IDS for different gate-source voltage $V_{gs}$ is significantly increased with optical illumination for photon flux densities of ${\Phi}=10^{15}\;and\;10^{17}/cm^2s$ compared to the dark condition. Further more, the drain-source current as a function of drain-source voltage $V_{DS}$ is evaluated to find the I-V characteristics for various pinch-off voltages $V_P$ for optimization of impurity flux density $Q_{Diff}$ by diffusion process. The resulting I-V characteristics also show that the diffusion process introduces less process-induced damage compared to ion implantation, which suffers from current reduction due to a large number of defects introduced by the ion implantation process. Further the results show significant increase in gate-source capacitance $C_{gs}$ and gate-drain capacitance $C_{gd}$ for optical illuminations, where the photo-induced voltage has a significant role on gate capacitances. The switching time ${\tau}$ of the OPFET device is computed for dark and illumination conditions. The switching time ${\tau}$ is greatly reduced by optical illumination and is also a function of device active layer thickness and corresponding impurity flux density $Q_{Diff}$. Thus it is shown that the diffusion process shows great potential for improvement of optoelectronic devices in quantum efficiency and other performance areas.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.485-488
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• 2004

As scaling down the cell channel length, the increment of B concentration in channel region is inevitable to overcome the punch-through, especially in flash memory cell with 90nm technology. This paper shows that the high dose ion implantation in channel cause the Si defect. which has been proved to be the major cause of the tailed Vth in distribution. And also mechanical stress due to SiN-anneal process can induce the Si dislocation. and get worse it. With decreasing the channel implantation dose, skipping the anneal and reducing the mechanical stress, Si defect problem is solved completely. We are verify first that the optimization of B concentration in channel must be certainly considered in order to improve Si defect. It is also certainly necessary to stabilize the distribution of cell Vth in the next generation of flash memory.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.3-4
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• 2005

Germanium nanocrystals(NCs) were formed in the silicon dioxide($SiO_2$) on Si layers by Ge implantation and rapid thermal annealing process. The density and mean size of Ge-NCs heated at $800^{\circ}C$ during 10 min were confirmed by High Resolution Transmission Electron Microscopy. Capacitance versus voltage(C-V) measurements of MOS capacitors with single $Al_2O_3$ capping layers were performed in order to study electrical properties. The C-V results exhibit large threshold voltage shift originated by charging effect in Ge-NCs, revealing the possibility that the structure is applicable to Nano Floating Gate Memory(NFGM) devices.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1995년도 추계학술대회 논문집
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• pp.48-51
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• 1995

We have developed the three dimensional mesh generator for three dimensional process simulation using the FEM(Finite Element Method). Tetrahedron element construct the presented three dimensional mesh, which is suitable for the simulation of three dimensional behavior of the LOCOS. The simulation of thermal oxidation is one of the problem in scale downed semiconductor processes. As three dimensional simulators use the huge size of the memory, we use the efficient method that generates the new nodes inside the growing oxide and removes the nodes nearby the SiO2/Si interface in silicon. The resented three dimensional mesh generator was designed to be used in various process simulations, for instance thermal oxidation, silicidation, nitridation, ion implantation, diffusion, and so on.

• 전자공학회논문지A
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• 제33A권7호
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• pp.127-133
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• 1996

In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photoresist reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate form both sides of the main gate. The poly-Si channel layer below the offset oxide is protected form the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of oru new device is the offset region due to the offset oxide. our experimental reuslts show that the offset region, due to the photoresist reflow process, has been sucessfully obtained in order to fabricate the offset gated poly-Si TFTs. The maximum ON/OFF ratio occurs at the L$_{off}$ of 1.1${\mu}$m and exceeds 1X10$^{6}$.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.451-458
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• 2006

The Chair of Display Technology at the University of Stuttgart develops various technologies for active matrix applications. Last year we presented an LTPS active matrix process without the need for ion implantation. This process is compared to other AM processes and the technological demands for different applications are discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권6호
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• pp.662-667
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• 2013

The effect of fluorine ions, which can be reacted with boron in high-doped BPSG, is investigated on the contact sidewall wiggling profile in semiconductor process. In the semiconductor device, there are many contacts on $p^+/n^+$ source and drain region. However these types of wiggling profile is only observed at the $n^+$ contact region. As a result, we find that the type of plug implantation dopant can affect the sidewall wiggling profile of contact. By optimizing the proper fluorine gas flow rate, both the straight sidewall profile and the desired electrical characteristics can be obtained. In this paper, we propose a fundamental approach to improve the contact sidewall wiggling profile phenomena, which mostly appear in high-doped BPSG on next-generation DRAM products.