• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.71-73
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• 2019

The output current of the Grid Connected Inverter (GCI) can be polluted with harmonics mainly due to i) dead time in switches, ii) non-linearity of switches, iii) grid harmonics, and iv) DC link fluctuation. Therefore, it is essential to design the robust Harmonic Compensation (HC) technique for the improvement of output current quality and fulfill the IEEE 1547 Total harmonics Distortion (THD) limit i.e. <5%. The conventional harmonic techniques often are complex in implementation due to their i) additional hardware needs, ii) complex structure, iii) difficulty in tuning of parameters, iv) current controller compatibility issues, and v) higher computational burden. In this paper, to eliminate the harmonics from the GCI output current, a novel Digital Lock-In Amplifier (DLA) based harmonic detection is proposed. The advantage of DLA is that it extracts the harmonic information accurately, which is further compensated by means of PI controller in feed forward manner. Moreover, the proposed HC method does not require additional hardware and it works with any current controller reference frame. To show the effectiveness of the proposed HC method a 5kW GCI prototype built in laboratory. The output current THD is achieved less than 5% even with 10% load, which is verified by simulation and experiment.

• Proceedings of the KIPE Conference
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• 2018.11a
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• pp.104-106
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• 2018

The harmonics and the DC offset in the grid can cause serious synchronization problems for grid connected inverters (GCIs) which leads not able to satisfy the IEEE 519 and p1547 standards in terms of phase and frequency variations. In order to guarantee the smooth and reliable synchronization of GCIs with the grid, Phase Locked Loop (PLL) is the crucial element. Typically, the performance of the PLL is assessed to limit the grid disturbances e.g. grid harmonics, DC Offset and voltage sag etc. To ensure the quality of GCI, the PLL should be precise in estimating the grid amplitude, frequency and phase. Therefore, in this paper a novel Robust PLL technique called Digital Lock-in Amplifier (DLA) PLL is proposed. The proposed PLL estimate the frequency variations and phase errors accurately even in the highly distorted grid voltage conditions like grid voltage harmonics, DC offsets and grid voltage sag. To verify the performance of proposed method, it is compared with other six conventional used PLLs (CCF PLL, SOGI PLL, SOGI LPF PLL, APF PLL, dqDSC PLL, MAF PLL). The comparison is done by simulations on MATLAB Simulink. Finally, the experimental results are verified with Single Phase GCI Prototype.

• Journal of Korea Society of Digital Industry and Information Management
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• v.19 no.2
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• pp.11-25
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• 2023

With the increasing advancement of VLSI technology, health care system is also developing to serve the humanity with better care. Therefore, biomedical implantable devices are one of the amazing important invention of scientist to collect data from the body cell for the diagnosis of diseases without any pain. This Biomedical implantable transceiver circuit has several important issues. Oscillator is one of them. For the design flexibility and complete transistor-based architecture ring oscillator is favorite to the oscillator circuit designer. This paper represents the design and analysis of the a 9-stage CMOS ring oscillator using cadence virtuoso tool in 180nm technology. It is also designed to generate the carrier signal of 403.5MHz frequency. Ring oscillator comprises of odd number of stages with a feedback circuit forming a closed loop. This circuit was designed with 9-stages of delay inverter and simulated for various parameters such as delay, phase noise or jitter and power consumption. The average power consumption for this oscillator is 9.32㎼ and average phase noise is only -86 dBc/Hz with the source voltage of 0.8827V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.7
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• pp.694-704
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• 2011

In this paper, we present a design of a 5th order Chebyshev interdigital band-pass filter using inverter and susceptance slope parameter values obtained from EM simulated multi-port Y-parameters. The shifted length of the resonator is determined when the frequency of the transmission zero is separated far away from the center frequency. For the initial dimensions of the interdigital filter, the filter is decomposed into the individual resonators, and the dimensions are obtained using EM Simulation of the decomposed resonators. However, the interdigital filter with the dimensions determined from the EM simulation of the decomposed resonators shows slightly distorted response from the desired frequency response due to the coupling between non-adjacent resonators. To obtain a EM simulation dataset, EM simulation for this filter is carried out by parameter sweep with constant ratio for the initial values. In this dataset, it is determined the final values for the filter by optimization. The fabricated filter by PCB shows an upper-shift of center frequency of about 70 MHz, which was caused by permittivity changed and tolerance of fabrication.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.7
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• pp.710-721
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• 2013

The noise prediction of motor driving system is one of the most important parts in EV/HEV, as the number of power electronic devices increases. This paper describes the mechanism of noise making process and proposes a simulation model of motor driving system for the prediction of the conducted noise. Theoretical calculations and model based simulations were carried out. DOD-dependent-battery parameters were extracted by AC analysis, and an inverter model including dynamic diode was used. Furthermore, 2-D EM tool was used for the motor modeling and was combined with the circuit models of battery and inverter. The simulated voltages, currents and spectrums in the motor driving system showed qualitatively meaningful results, suggesting the validness of the suggested modeling methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.9-14
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• 2007

In this article, the organic integrated circuits such as inverter, ring oscillator, NAND and NOR gates, and rectifier have been fabricated on PEN substrate by using pentacene TFTs, The OTFTs used bottom contact structure and produced the average mobility of 0.26 $cm^2/V.sec$ and on/off current ratio of $10^5$. All circuits successfully worked as the simulation results. Especially, the rectifier was able to operate up to 1 MHz input AC signals, and ring oscillator exhibited oscillation frequency of 1MHz at 40 V. Based on the results of organic integrated circuits we could confirm the possibility of the low cost RFID tags and flexible display with OTFTs.

• Journal of the Korea Society of Computer and Information
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• v.19 no.10
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• pp.151-158
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• 2014

In this paper, we have designed and implemented the 'N-screen based solar power monitoring system' using N-screen technology by improving the existing monitoring system that can only be accessed or controlled by PC. The HW of the system is consists of solar power modules, inverter, and relay server. And SW is implemented in consideration of the following three points. First, we applied the N-screen technology in order to support various devices. Second, we applied 1:N communication technology that multiple devices can be connected simultaneously to the relay server. Third, we also considered the security problems between server and devices. The final system has been evaluated through the operational test and received good reviews from the technical and economic point. In the future, we are expecting that this technology will replace the existing monitoring systems in various fields, like smart home, smart building, smart city, smart industry, and smart agriculture, etc.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.3
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• pp.539-546
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• 2018

Recently, as the solar power generation market is rapidly increasing, interest is focused on research for minimizing the output of the solar cell module. The role of the power optimizer is important when inconsistencies occur in photovoltaic power generation. In the conventional system, centralized inverter method and microinverter method are mainly used. In this paper, we analyze the problem of power generation efficiency loss due to the incompatibility of existing system configuration methods. We also proposed a module - type power compensation method that can improve the mismatch caused by shading. The proposed module - based power optimizer is implemented and compared with the existing operation method. From the simulation result, it was confirmed that the efficiency of the proposed operation method is improved compared to the existing method.

• Transactions of the Korean Society of Automotive Engineers
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• v.22 no.6
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• pp.23-30
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• 2014

This paper proposes a dead time compensation method for an AC motor drive using phase current polarity information which is detected based on a digital programmable low-pass filter (PLPF). The polarity detection using the PLPF is an alternative solution of a conventional method which uses a general low-pass filter (LPF) and hysteresis bands in order to avoid jittering due to noises. The PLPF not only adjusts its cutoff frequency according to the synchronous frequency of AC motors but also eliminates a gain attenuation and phase delay which are main problems of the general LPF. Through the PLPF, a fundamental component signal without gain and phase distortions is extracted from the measured raw current signal with noise. By use of the fundamental component, the polarity of current is effectively detected by reducing the hysteresis band. Finally, the proposed method compensates the dead time effects by adding or subtracting average voltage value to voltage references of the controller according to the detected current polarity information. The proposed compensation method is experimentally verified by compared with the conventional method.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.52 no.2
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• pp.68-79
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• 2003

We estimated harmonics on power system of AC railway based on quantitatively measured harmonics and investigated the need of facilities for harmonics reduction. In order to analysis harmonics which inflow into power system due to increase in collector voltages and harmonic currents generated from the train when the railway is in operation, the railway system Is sectioned into power supply, railway line, AT, sectioning Post and subsectioning post. For analysis of extension of currents resulting from the railway loads, PWM converter, VVVF inverter and the feeder system are modeled based on the dynamic node technique(DNT). In order to test the usefulness of the DNT for analysis of harmonic effects, the measured harmonic currents and harmonic magnification ratios at the S/K substation are compared with simulation results using DNT modelling, which include the results for two cases with and without filters for suppression of harmonic currents. When 8 cars(4M4T) are in operation, the total sum of harmonic currents resulting from the train at M and T phases, which inflow into the substation along with the railway line, is calculated. Using the harmonics analysis program for railway feeder system with these data, the total harmonic distortion factor(710) at the outgoing point of KEPCO substation is computed. The calculation shows that when the maximum THD at the receiving point of H/K substation was 0.0443% which is much lower than 1.5% which is the allowable value of KEPCO at 154kV as well as IEEE-519 above 132kV This result indicates that any measure for harmonics reduction in Incheon International Airport Railway is not needed.