• Information and Communications Magazine
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• v.25 no.12
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• pp.10-18
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• 2008

In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-core platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720x480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400MHz@30fps with CIF(Common Intermediated format) and about 100k per core for H.264 decoder.

• Journal of Information Processing Systems
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• v.11 no.3
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• pp.389-405
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• 2015

Most traditional database systems exploit a record-oriented model where the attributes of a record are placed contiguously in a hard disk to achieve high performance writes. However, for read-mostly data warehouse systems, the column-oriented database has become a proper model because of its superior read performance. Today, flash memory is largely recognized as the preferred storage media for high-speed database systems. In this paper, we introduce a column-oriented database model based on flash memory and then propose a new column-aware flash indexing scheme for the high-speed column-oriented data warehouse systems. Our index management scheme, which uses an enhanced $B^+$-Tree, achieves superior search performance by indexing an embedded segment and packing an unused space in internal and leaf nodes. Based on the performance results of two test databases, we concluded that the column-aware flash index management outperforms the traditional scheme in the respect of the mixed operation throughput and its response time.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.6
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• pp.21-28
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• 2008

In this paper, we proposed an algorithm that reduces call setup time between the IP PBXs installed in the main office and several branch offices. In the IP PBXs installed in branch offices, we prepare some internal memory spaces, and they keep the frequently used extension numbers and the corresponding IP PBX's addresses. In order to call an extension number registered to the other remote IP PBX from an extension number registered to the local IP PBX, the local PBX searches for the destined extension from its internal memory first. If the extension is found, then the local PBX uses its corresponding IP PBX address stored along with the extension, instead of making a query to the main office's IP PBX. By this technique, we could shorten the average call setup time and verified it by an experiment.

• Journal of Korea Multimedia Society
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• v.12 no.10
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• pp.1374-1385
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• 2009

Recently, advances in speed of the CPU have for out-paced advances in memory speed. Main-memory access is increasingly a performance bottleneck for main-memory database systems. To reduce memory access speed, cache memory have incorporated in the memory subsystem. However cache memories can reduce the memory speed only when the requested data is found in the cache. We propose a new cache sensitive T-tree index structure called as $CST^*$-tree for range query search. The $CST^*$-tree reduces the number of cache miss occurrences by loading the reduced internal nodes that do not have index entries. And it supports the sequential access of index entries for range query by connecting adjacent terminal nodes and internal index nodes. For performance evaluation, we have developed a cost model, and compared our $CST^*$-tree with existing CST-tree, that is the conventional cache sensitive T-tree, and $T^*$-tree, that is conventional the range query search T -tree, by using the cost model. The results indicate that cache miss occurrence of $CST^*$-tree is decreased by 20~30% over that of CST-tree in a single value search, and it is decreased by 10~20% over that of $T^*$-tree in a range query search.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9A
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• pp.1442-1450
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• 1999

In this paper, we present an efficient hardware architecture for the frame memory of the MPEG-2 video encoder. Both the total size of internal buffers and the number of logic gates are reduced by the proposed memory map which can provide an effective interface between MPEG-2 video encoder and the external DRAM. Furthermore, the proposed scheme can reduce the DRAM access time. To realize the frame memory hardware,$0.5\mu\textrm{m}$, VTI, vemn5a3 standard cell library is used. VHDL simulator and logic synthesis tool are used for hardware design and RTL (register transfer level) function verification. The frame memory hardware emulator of the proposed architecture is designed for gate-level function verification. It is expected that the proposed frame memory hardware using VHDL can achieve suitable performance for MPEG-2 MP@ML.

• ETRI Journal
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• v.31 no.6
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• pp.784-794
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• 2009

We present a full HD (1080p) H.264/AVC High Profile hardware encoder based on fast motion estimation (ME). Most processing cycles are occupied with ME and use external memory access to fetch samples, which degrades the performance of the encoder. A novel approach to fast ME which uses shared multibank memory can solve these problems. The proposed pixel subsampling ME algorithm is suitable for fast motion vector searches for high-quality resolution images. The proposed algorithm achieves an 87.5% reduction of computational complexity compared with the full search algorithm in the JM reference software, while sustaining the video quality without any conspicuous PSNR loss. The usage amount of shared multibank memory between the coarse ME and fine ME blocks is 93.6%, which saves external memory access cycles and speeds up ME. It is feasible to perform the algorithm at a 270 MHz clock speed for 30 frame/s real-time full HD encoding. Its total gate count is 872k, and internal SRAM size is 41.8 kB.

• Journal of IKEEE
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• v.17 no.2
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• pp.202-207
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• 2013

This paper implemented the conventional FAST and BRIEF algorithm as hardware on Zynq-7000 SoC Platform. Previous feature-based hardware accelerator is mostly implemented using the SIFT or SURF algorithm, but it requires excessive internal memory and hardware cost. The proposed FAST & BRIEF accelerator reduces approximately 57% of internal memory usage and 70% of hardware cost compared to the conventional SIFT or SURF accelerator, and it processes 0.17 pixel per Clock.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.2
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• pp.73-81
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• 2007

We give two weaknesses of a recently proposed streamcipher MICKEY. We show time-memory-data tradeoff is applicable. We also show that the state update function reduces entropy of the internal state as it is iterated, resulting in keystreams that start out differently but become merged together towards the end.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.119-122
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• 2003

This paper presents an efficient huffman decoding method based on the multiple branch technique. In the proposed search method, the internal node which does not contain a leaf node are removed for decrease the searching time and the memory consumption. The proposed search method gives 44％ of improved in searching time and 34％ of decreased in memory requirement compared to the binary search method.

• Proceedings of the Korea Database Society Conference
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• 2001.11a
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• pp.239-256
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• 2001

1. 일관성 (Consistency)과 표준화(Standardization) 2. 유용한 피드백의 제공 3 실수에 대한 대응책(Easy Error Handling) 4. 자기 위치정보의 제공(Internal Locus of Control) 5. 단기 기억부담의 최소화(Minimal Memory Load) (중략)