• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.63-70
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• 2008

In this paper, a smart sensor system for the MEMS pressure sensor was developed. A compensation algorithm and programmable calibration circuits were presented to eliminate errors caused by temperature drift of piezoresistive pressure sensors in itself. This system consisted of signal conditioning, calibration, temperature detection, microprocessor, and communication parts and these were integrated into a SOC. A RS-232 interface was employed for monitoring and control of a smart sensor system. The area of fabricated IC is $4.38{\times}3.78\;mm^2$ and a $0.35{\mu}m$ high voltage CMOS process was used. Compensation error for temperature drift of 50 KPa pressure sensors was measured into ${\pm}0.48%$ in the range of $-40^{\circ}C{\sim}150^{\circ}C$. Total power consumption was 30.5 mW.

• Korean Journal of Materials Research
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• v.20 no.6
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• pp.319-325
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• 2010

3-D IC integration enables the smallest form factor and highest performance due to the shortest and most plentiful interconnects between chips. Direct metal bonding has several advantages over the solder-based bonding, including lower electrical resistivity, better electromigration resistance and more reduced interconnect RC delay, while high process temperature is one of the major bottlenecks of metal direct bonding because it can negatively influence device reliability and manufacturing yield. We performed quantitative analyses of the interfacial properties of Al-Al bonds with varying process parameters, bonding temperature, bonding time, and bonding environment. A 4-point bending method was used to measure the interfacial adhesion energy. The quantitative interfacial adhesion energy measured by a 4-point bending test shows 1.33, 2.25, and $6.44\;J/m^2$ for 400, 450, and $500^{\circ}C$, respectively, in a $N_2$ atmosphere. Increasing the bonding time from 1 to 4 hrs enhanced the interfacial fracture toughness while the effects of forming gas were negligible, which were correlated to the bonding interface analysis results. XPS depth analysis results on the delaminated interfaces showed that the relative area fraction of aluminum oxide to the pure aluminum phase near the bonding surfaces match well the variations of interfacial adhesion energies with bonding process conditions.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.27-31
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• 2015

Thermal management becomes a key technology as the power density of high performance and high density devices increases. Conventional heat sink or TIM methods will be limited to resolve thermal problems of next-generation IC devices. Recently, to increase heat flux through high powered IC devices liquid cooling system has been actively studied. In this study a chip-level liquid cooling system with TSV and microchannel was fabricated on Si wafer using DRIE process and analyzed the cooling characteristics. Three different TSV shapes were fabricated and the effect of TSV shapes was analyzed. The shape of liquid flowing through microchannel was observed by fluorescence microscope. The temperature differential of liquid cooling system was measured by IR microscope from RT to $300^{\circ}C$.

• Journal of Welding and Joining
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• v.17 no.1
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• pp.124-132
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• 1999

Thermal fatigue strength of the solder joints is the most critical issue for TSOP(Thin Small Outline Package) because the leads of this package are extremely short and thermal deformation cannot be absorbed by the deflection of the lead. And the TSOP body can be subject to early fatigue failures in thermal cycle environments. This paper was discussed distribution of thermal stresses at near the joint between silicon chip and die pad and investigated their reliability of solder joints of TSOP with 42 alloy clad lead frame on printed circuit board through FEM and 3 different thermal cycling tests. It has been found that the stress concentration around the encapsulated edge structure for internal crack between the silicon chip and Cu alloy die pad. And using 42 alloy clad, The reliability of TSOP body was improved. In case of using 42 alloy clad die pad(t=0.03mm). $$\sigma$_{VMmax}$ is 69Mpa. It is showed that 15% improvement of the strength in the TSOP body in comparison with using Cu alloy die pad $($\sigma$_{VMmax}$=81MPa). In solder joint of TSOP, the maximum equivalent plastic strain and Von Mises stress concentrate on the heel of solder fillet and crack was initiated in it's region and propagated through the interface between lead and solder. Finally, the modified Manson-Coffin equation and relationship of the ratio of $N_{f}$ to nest(η) and cumulative fracture probability(f) with respect to the deviations of the 50% fracture probability life $(N_{f 50%})$ were achieved.

• Journal of the Korean Electrochemical Society
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• v.8 no.1
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• pp.1-5
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• 2005

Electric double layer capacitors(EDLCS) based on the charge stored at the interface between a hi팀 surface area carbon electrode and an organic electrolyte solution are widely used as a maintenance-free power source for IC memories and microcomputers. The achievement of the excellent performance of the capacitor requires an electrolyte solution which provides high conductivities over a wide temperature range and good electrochemical stabilities to allow the capacitor to be operated at high voltage. The electrochemical capacitor using a carbon material as electrodes and using an organic electrolyte with $1M-LiPF_6$ in PC-GBL-DEC(volume ratio 1:1:2) has specific capacitance of 64F/g.

• Journal of IKEEE
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• v.20 no.3
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• pp.260-264
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• 2016

The MAX77846, which is compatible with MAX77826, is a sub-power management IC (PMIC) for the latest Wearable Watch and 3G/4G smart phones. The MAX77846 contains N-MOSFET (N channel Metal-Oxide Semiconductor Field-Effect Transistor), a high-efficiency regulator, and comparator, etc to power up peripherals. The MAX77846 also provides power on/off control logic for complete flexibility and an $I^2C$ (Inter Integrated Circuit) serial interface to program individual regulator output voltages. In this paper, the simplified power macro-model based on MAX77846 is designed to verify the performance of the battery voltage in terms of current and time, and simulated by using of the LTspice. In addition, it is verified how much time can the charged battery capacity for Samsung Galaxy Gear 2 be used to operate a specified function after measuring the currents flowing to carry out the main functions in real time, which will be applicable to design parameters for the advanced power module

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.31-38
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• 2005

The architecture and the implementation details of a UTMI(USB2.0 Transceiver Macrocell Interface) compatible USB2.0 transceiver chip were presented. To confirm the validation of the incoming data in noisy channel environment, a squelch state detector and a current mode Schmitt-trigger circuit were proposed. A current mode output driver to transmit 480Mbps data on the USB cable was designed and an on-die termination(ODT) which is controlled by a replica bias circuit was presented. In the USB system using plesiochronous clocking, to compensate for the frequency difference between a transmitter and a receiver, a synchronizer using clock data recovery circuit and FIFO was designed. The USB cable was modeled as the lossy transmission line model(W model) for circuit simulation by using a network analyzer measurements. The USB2.0 PHY chip was implemented by using 0.25um CMOS process and test results were presented. The core area excluding the IO pads was $0.91{\times}1.82mm^2$. The power consumptions at the supply voltage of 2.5V were 245mW and 150mW for high-speed and full-speed operations, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.31-38
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• 2008

This paper describes sensor network system implementation for the IEEE 1451.2 standard which guarantees compatibilities between various wired sensors. The proposed system consists of the Network Capable Application Processor(NCAP) in the IEEE 1451.0, the Transducer Independent Interface(TII) in the IEEE 1451.2, the Transducer Electronic Data Sheet(TEDS) and sensors. The research goal of this study is to minimize and optimize system complexity for IC design. The NCAP is implemented using C language in personal computer environment. TII is used in the parallel port between PC and an FPGA application board. Transducer is implemented using Verilog on the FPGA application board. We verified the proposed system architecture based on the standards.

• Journal of Satellite, Information and Communications
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• v.9 no.1
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• pp.13-16
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• 2014

In applying LCD to TV application, one of the most significant factors to be improved is image sticking on the moving picture. LCD is different from CRT in the sense that it's continuous passive device, which holds images in entire frame period, while impulse type device generate image in very short time. To reduce image sticking problem related to hold type display mode, we made an experiment to drive TN-LCD like CRT. We made articulate images by fast refreshing images, and we realized the ratio of refresh time by counting between on time and off time for video signal input during 1 frame (16.7ms). Conventional driving signal cannot follow fast on-off speed, so we evaluated new signal generator using SDI (Serial Data Interface) mode signal generator. We realized articulate image generation similar to CRT by high fast full HD (High Definition) signals and TN-LCD overdriving. As a result, reduced image sticking phenomenon was validated by naked eye and response time measurement.

• Korean Journal of Materials Research
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• v.18 no.4
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• pp.204-210
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• 2008

$1.5\;{\mu}m$-thick copper films deposited on silicon wafers were successfully bonded at $415^{\circ}C$/25 kN for 40 minutes in a thermo-compression bonding method that did not involve a pre-cleaning or pre-annealing process. The original copper bonding interface disappeared and showed a homogeneous microstructure with few voids at the original bonding interface. Quantitative interfacial adhesion energies were greater than $10.4\;J/m^2$ as measured via a four-point bending test. Post-bonding annealing at a temperature that was less than $300^{\circ}C$ had only a slight effect on the bonding energy, whereas an oxygen environment significantly deteriorated the bonding energy over $400^{\circ}C$. This was most likely due to the fast growth of brittle interfacial oxides. Therefore, the annealing environment and temperature conditions greatly affect the interfacial bonding energy and reliability in Cu-Cu bonded wafer stacks.