• Title/Summary/Keyword: interconnection network

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Embedding Algorithms Hypercube, HCN, and HFN into HFCube Interconnection Networks (상호연결망 HFCube와 하이퍼큐브, HCN, HFN 사이의 임베딩 알고리즘)

  • Kim, Jong-Seok;Lee, Hyeong-Ok
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.6
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    • pp.1361-1368
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    • 2014
  • In this paper, we analyze emddings among HFCube(n,n), HCN(n,n), HFN(n,n) with lower network cost than that of Hypercube. The results are as follows. We propose that $Q_{2n}$ can be embedded into HFCube(n,n) with dilation 5, congestion 2. HCN(n,n) and HFN(n,n) are subgraphs of HFCube(n,n). HFCube(n,n) can be embedded into HFN(n,n) with dilation 3. HFCube(n,n) can be embedded into HCN(n,n) with dilation O(n). The results will be helpful to analyze several efficient properties in each interconnection network.

A Switch Wrapper Design for an AMBA AXI On-Chip-Network (AMBA AHB와 AXI간 연동을 위한 Switch Wrapper의 설계)

  • Yi, Jong-Su;Chang, Ji-Ho;Lee, Ho-Young;Kim, Jun-Seong
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.869-872
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    • 2005
  • In this paper we present a switch wrapper for an AMBA AXI, which is an efficient on-chip-network interface compared to bus-based interfaces in a multiprocessor SoC. The AXI uses an idea of NoC to provide the increasing demands on communication bandwidth within a single chip. A switch wrapper for AXI is located between a interconnection network and two IPs connecting them together. It carries out a mode of routing to interconnection network and executes protocol conversions to provide compatibility in IP reuse. A switch wrapper consists of a direct router, AHB-AXI converters, interface modules and a controller modules. We propose the design of a all-in-one type switch wrapper.

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Embedding between a Macro-Star Graph and a Matrix Star Graph (매크로-스타 그래프와 행렬 스타 그래프 사이의 임베딩)

  • Lee, Hyeong-Ok
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.3
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    • pp.571-579
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    • 1999
  • A Macro-Star graph which has a star graph as a basic module has node symmetry, maximum fault tolerance, and hierarchical decomposition property. And, it is an interconnection network which improves a network cost against a star graph. A matrix star graph also has such good properties of a Macro-Star graph and is an interconnection network which has a lower network cost than a Maco-Star graph. In this paper, we propose a method to embed between a Macro-Star graph and a matrix star graph. We show that a Macro-Star graph MS(k, n) can be embedded into a matrix star graph MS\ulcorner with dilation 2. In addition, we show that a matrix star graph MS\ulcorner can be embedded into a Macro-Star graph MS(k,n+1) with dilation 4 and average dilation 3 or less as well. This result means that several algorithms developed in a star graph can be simulated in a matrix star graph with constant cost.

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Parallel Multistage Interconnection Switching Network for Broadband ISDN (광대역 ISDN을 위한 병렬 다단계 상호 연결 스위치 네트워크)

  • 박병수
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.3 no.4
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    • pp.274-279
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    • 2002
  • ATM packet switching technologies for the purpose of the B-ISDN service are focused on high performance which represents good qualities on throughput, packet loss, and packet delay. ATM switch designs on a class of parallel interconnection network have been researched. But these are based on the self-routing function of it. It leads to conflict with each other, and to lose the packets. Therefore, this paper proposes the method based on Sort-Banyan network should be adopted for optimal routing algorithm. It is difficult to expect good hardware complexity. For good performance, a switch design based on the development of new routing algorithm is required. For the design of switch network, the packet distributor and multiplane are proposed. They prevent each packet from blocking as being transmitted selectively by two step distributed decision algorithm. This switch will be proved to be a good performance switch network that internal blocking caused from self-routing function is removed. Also, it is expected to minimize the packet loss and decrease the packet delay according to packet transmission.

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A Comparative Analysis of Interconnection Charging Methods Between the Telephony Networks and IP Phone Networks (전화망과 IP Phone망간 합리적인 정산방안 비교 연구)

  • Moon Joon-seo;Park Myeong-cheol;Lee Hong-kyu;Kweon Soo-cheon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.10B
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    • pp.676-688
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    • 2005
  • We introduced mathematical economic analysis model for understanding the fairness of charge from VoIP providers for interconnection of access network. In order to set up this model we made four assumptions predictable in the real world. Also we proposed two accounting method that is flat-rate-pricing and usage-based-pricing and tried to propose which method is more desirable to charge for interconnection on the basis of social welfare and activation of market competitiveness. The outcome of this study includes the reasonable accounting method for interconnection between telephone network and IP Phone network which is most effective to ensure the social welfare and market competitiveness

Symmetry Analysis of Interconnection Networks and Impolementation of Drawing System (상호연결망의 대칭성분석 및 드로잉 시스템 구현)

  • Lee, Yun-Hui;Hong, Seok-Hui;Lee, Sang
    • Journal of KIISE:Computer Systems and Theory
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    • v.26 no.11
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    • pp.1353-1362
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    • 1999
  • 그래프 드로잉이란 추상적인 그래프를 시각적으로 구성하여 2차원 평면상에 그려주는 작업으로 대칭성은 그래프 드로잉시 고려해야 하는 미적 기준들 중에서 그래프의 구조 및 특성을 표현해주는 가장 중요한 기준이다. 그러나 일반 그래프에서 대칭성을 찾아 그려 주는 문제는 NP-hard로 증명이 되어 있기 때문에 현재까지는 트리, 외부평면 그래프, 직병렬 유향 그래프나 평면 그래프 등으로 대상을 한정시켜 연구가 진행되어 왔다. 본 논문에서는 병렬 컴퓨터나 컴퓨터 네트워크 구조를 가시화 시키기 위하여 많이 사용되는 그래프인 상호연결망(interconnection network)의 대칭성을 분석하고 분석된 대칭성을 최대로 보여주는 대칭 드로잉 알고리즘을 제안하였다. 그리고 이를 기반으로 하여 상호연결망의 기존 드로잉 방법들과 본 논문에서 제안한 대칭 드로잉 등 다양한 드로잉을 지원하는 WWW 기반의 상호연결망 드로잉 시스템을 구현하였다.Abstract Graph drawing is constructing a visually-informative drawing of an abstract graph. Symmetry is one of the most important aesthetic criteria that clearly reveals the structures and the properties of graphs. However, the problem of finding geometric symmetry in general graphs is NP-hard. So the previous work has focused on the subclasses of general graphs such as trees, outerplanar graphs, series-parallel digraphs and planar graphs.In this paper, we analyze the geometric symmetry on the various interconnection networks which have many applications in the design of computer networks, parallel computer architectures and other fields of computer science. Based on these analysis, we develope algorithms for constructing the drawings of interconnection networks which show the maximal symmetries.We also design and implement Interconnection Network Drawing System (INDS) on WWW which supports the various drawings including the conventional drawings and our suggested symmetric drawings.

A Study on Validity of Interconnection Policy Revision with the Advent of 3G Mobile Network (3G 이동통신망 출현에 따른 접속료 정책의 개정 타당성에 관한 연구)

  • Lee, Sang-Yeop;Park, Myeong-Cheol;Hyun, Tchang-Hee
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.12B
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    • pp.1099-1111
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    • 2006
  • As W-CDMA R5(HSDPA) service became recently commercialized in Korea, there is increasing demand for new pricing methodology for the 3G mobile interconnection at the earliest possible time. However, it is hard to find any case of systematic study on it. In this paper, a synthetic investigation into the three aspects of new mobile telecommunication service - technology, market, and regulation - is conducted to verify the validity of new interconnection pricing methodology. As the findings of this research indicate, given the several technological limits of 3G, speed of mobile telecommunication industry evolution, the problem of verifying ex-ante regulations' validity, and the cases of some foreign countries, it is suggested that immediate revision of interconnection policy is not sensible and that the revision is more desirable to be postponed until the maturity of the 3G market or the adoption of All-IP network.

Performance Evaluation of a Multistage Interconnection Network with Buffered axa Switches under Hot-spot Environment (핫스팟 상황 하에서 출력 버퍼형 axa 스위치로 구성된 다단 연결망의 성능분석)

  • Kim Jung-Yoon;Shin Tae-Zi;Yang Myung-Kook
    • Proceedings of the Korean Information Science Society Conference
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    • 2005.11a
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    • pp.166-168
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    • 2005
  • 본 논문에서는, axa 출력 버퍼 스위치로 구성된 핫스팟이 발생된 상황 하에서 다단 연결 망(Multistage interconnection Network, MIN)의 성능 예측 모형을 제안하였다. 제안한 성능 예측 오형은 먼저 네트워크 내부 임의 스위치 입력 단에 유입되는 데이터 패킷이 스위치 내부에서 전송되는 유형을 확률적으로 분석하여 설계하였다. 성능분석 모형은 스위치에 장착된 버퍼의 개수와 무관하게 버퍼를 장착한 axa 스위치의 성능, 네트워크 정상상태 처리율(Normalized Throughput, NT)과 네트워크 지연시간(Network Delay)의 예측이 가능하고, 나아가서 이들로 구성진 모든 종류의 다단 연결망 성능 분석에 적용이 용이하다. 제안한 수학적 성능 분석 연구의 실효성 검증을 위하여 병행된 시뮬레이션 결과는 상호 미세한 오차 범위 내에서 모형의 예측 데이터와 일치하는 결과를 보여 분석 모형의 타당성을 입증하였다.

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Using Minimal Path Sets for the Evaluation of the Reliability of DRDT Interconnection $Networks^+$

  • Lim , Hae-Hak;Lee, Chong-Hyung;Cho, Byung-Yup
    • Journal of Korean Society for Quality Management
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    • v.28 no.1
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    • pp.105-118
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    • 2000
  • In this paper, we consider an interconnection network, DRDT (Dual Receive Dual Transmit), that is a double-loop ring topology and adopts the concept of multiple packets transmission. For three types of DRDT configurations, we investigate some properties related to path sets and discuss the method for finding minimal path sets. Using the concept of the terminal reliability and the path sets approach, we evaluate the reliability of the DRDT networks and compare them with a single ring network and a unidirectional double-loop ring network.

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Analysis of Various Characteristics of the Half Pancake Graph (하프팬케익 그래프의 다양한 성질 분석)

  • Seo, Jung-Hyun;Lee, HyeongOk
    • Journal of Korea Multimedia Society
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    • v.17 no.6
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    • pp.725-732
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    • 2014
  • The Pancake graph is node symmetric and useful interconnection network in the field of data sorting algorithm. The Half Pancake graph is a new interconnection network that reduces the degree of the Pancake graph by approximately half and improves the network cost of the Pancake graph. In this paper, we analyze topological properties of the Half Pancake graph $HP_n$. Fist, we prove that $HP_n$ has maximally fault tolerance and recursive scalability. In addition, we show that in $HP_n$, there are isomorphic graphs of low-dimensional $HP_n$. Also, we propose that the Bubblesort $B_n$ can be embedded into Half Pancake $HP_n$ with dilation 5, expansion 1. These results mean that various algorithms designed for the Pancake graph and the Bubble sort graph can be executed on $HP_n$ efficiently.