• Industrial Engineering and Management Systems
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• 제13권1호
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• pp.52-66
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• 2014

Promotion of a closed-loop supply chain requires disassembly systems that recycle end-of-life (EOL) assembled products. To operate the recycling disassembly system, parts selection is environmentally and economically carried out with non-destructive or destructive disassembly, and the recycling rate of the whole EOL product is determined. As the number of disassembled parts increases, the recycling rate basically increases. However, the labor cost also increases and brings lower profit, which is the difference between the recovered material prices and the disassembly costs. On the other hand, since the precedence relationships among disassembly tasks of the product also change with the parts selections, it is also required to optimize allocation of the tasks in designing a disassembly line. In addition, because information is required for such a design, the recycling rate, profit of each part and disassembly task times take precedence among the disassembly tasks. However, it is difficult to obtain that information in advance before collecting the actual EOL product. This study proposes and analyzes an optimal disassembly system design using integer programming with the environmental and economic parts selection (Igarashi et al., 2013), which harmonizes the recycling rate and profit using recyclability evaluation method (REM) developed by Hitachi, Ltd. The first stage involves optimization of environmental and economic parts selection with integer programming with ${\varepsilon}$ constraint, and the second stage involves optimization of the line balancing with integer programming in terms of minimizing the number of stations. The first and second stages are generally and mathematically formulized, and the relationships between them are analyzed in the cases of cell phones, computers and cleaners.

• 통합자연과학논문집
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• 제12권2호
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• pp.44-46
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• 2019

In this paper, we study a ratio variation of Nicomachus' theorem by computing ${\sum\limits_{k=1}^{n}}[rk]$ and ${\sum\limits_{k=1}^{n}}[rk]^3$, where r is a rational number.

• Journal of applied mathematics & informatics
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• 제24권1_2호
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• pp.313-323
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• 2007

The equitable total chromatic number ${\chi}_{et}(G)$ of a graph G is the smallest integer ${\kappa}$ for which G has a total ${\kappa}$-coloring such that the number of vertices and edges in any two color classes differ by at most one. In this paper, we determine the equitable total chromatic number of one class of the graphs.

• ETRI Journal
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• 제27권5호
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• pp.617-627
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• 2005

This paper proposes an efficient scalar multiplication algorithm for hyperelliptic curves, which is based on the idea that efficient endomorphisms can be used to speed up scalar multiplication. We first present a new Frobenius expansion method for special hyperelliptic curves that have Gallant-Lambert-Vanstone (GLV) endomorphisms. To compute kD for an integer k and a divisor D, we expand the integer k by the Frobenius endomorphism and the GLV endomorphism. We also present improved scalar multiplication algorithms that use the new expansion method. By our new expansion method, the number of divisor doublings in a scalar multiplication is reduced to a quarter, while the number of divisor additions is almost the same. Our experiments show that the overall throughputs of scalar multiplications are increased by 15.6 to 28.3 % over the previous algorithms when the algorithms are implemented over finite fields of odd characteristics.

• Journal of Magnetics
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• 제22권1호
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• pp.29-33
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• 2017

We report a micromagnetic numerical study on different quasi-crystal formations of magnetic vortices in a rich variety of dynamic transient states in soft magnetic nano-disks. Only the application of spin-polarized dc currents to a single magnetic vortex leads to the formation of topological-soliton quasi-crystals composed of different configurations of skyrmions with positive and negative half-integer numbers (magnetic vortices and antivortices). Such topological object formations in soft magnets, not only in the absence of Dzyaloshinskii-Moriya interaction but also without magnetocrystalline anisotropy, are discussed in terms of two different topological charges, the winding number and the skyrmion number. This work offers an insight into the dynamic topological-spin-texture quasi-crystal formations in soft magnets.

• 대한수학회보
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• 제60권4호
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• pp.863-872
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• 2023

Let n ⩾ 2 be an integer, we denote the smallest integer b such that gcd {(ⁿ_k) : b < k < n - b} > 1 as b(n). For any prime p, we denote the highest exponent α such that p^α | n as v_p(n). In this paper, we partially answer a question asked by Hong in 2016. For a composite number n and a prime number p with p | n, let n = a_mp^m + r, 0 ⩽ r < p^m, 0 < a_m < p. Then we have $$v_p\(\text{gcd}\{\(n\\k\)\;:\;b(n)1\}\)=\{\array{1,&&a_m=1\text{ and }r=b(n),\\0,&&\text{otherwise.}}$$

• 호남수학학술지
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• 제37권4호
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• pp.529-547
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• 2015

In this paper, we proved some properties of the greatest expanded numbers, and give the method to determine the greatest expanded numbers and find the integer x for which $S_{q,p}(x)-x$ is the largest. Additionally, we provide an algorithm to find the greatest expanded number.

• 대한수학회논문집
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• 제31권3호
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• pp.447-450
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• 2016

Let $F_n$ and $L_n$ be the nth Fibonacci number and Lucas number, respectively. The order of appearance of m in the Fibonacci sequence, denoted by z(m), is the smallest positive integer k such that m divides $F_k$. Marques obtained the formula of $z(L^k_n)$ in some cases. In this article, we obtain the formula of $z(L^k_n)$ for all $n,k{\geq}1$.

• 한국정보통신학회논문지
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• 제12권7호
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• pp.1218-1226
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• 2008

반도체 집적 기술의 발달과 컴퓨터에서 멀티미디어 기능의 사용이 많아지면서 보다 많은 기능들이 하드웨어로 구현되기를 원하는 요구가 증가되고 있다. 그래서 현재 사용되는 대부분의 32 비트 마이크로프로세서는 정수 곱셈기를 하드웨어로 구현하고 있다. 그러나 나눗셈기는 기존의 알고리즘인 SRT 알고리즘의 방식이 하드웨어 구현상의 복잡도와 느린 동작 속도로 인해 특정 마이크로프로세서에 한해서만 하드웨어로 구현되고 있다. 본 논문에서는 'w bit $\times$ w bit = 2w bit' 곱셈기를 사용하여 $\frac{N}{D}$ 정수 나눗셈을 수행하는 알고리즘을 제안한다. 즉, 제수 D 의 역수를 구하고 이를 피제수 N 에 곱해서 정수 나눗셈을 수행한다. 본 논문에서는 제수 D 가 '$D=0.d{\times}2^L$, 0.5<0.d<1.0'일 때, '$0.d{\times}1.g=1+e$, $e<2^{-w}$'가 되는 '$\frac{1}{D}$'의 근사 값 '$1.g{\times}2^{-L}$'을 가칭 상역수라고 정의하고, 상역수를 구하는 알고리즘을 제안하고, 이렇게 구한 상역수 '$1.g{\times}2^{-L}$'을 피제수 N에 곱하여 $\frac{N}{D}$ 정수 나눗셈을 수행한다. 제안한 알고리즘은 정확한 역수를 계산하기 때문에 추가적인 보정이 요구되지 않는다. 본 논문에서 제안하는 알고리즘은 곱셈기만을 사용하므로 마이크로프로세서를 구현할 때 나눗셈을 위한 추가적인 하드웨어가 필요 없다. 그리고 기존 알고리즘인 SRT 방식에 비해 빠른 동작속도를 가지며, 워드 단위로 연산을 수행하기 때문에 기존의 나눗셈 알고리즘보다 컴파일러 작성에도 적합하다. 따라서, 본 논문의 연구 결과는 마이크로프로세서 및 하드웨어 크기에 제한적인 SOC(System on Chip) 구현 등에 폭넓게 사용될 수 있다.

• 대한전자공학회논문지TC
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• 제44권2호
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• pp.62-68
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• 2007

본 논문에서는 메모리와 곱셈기가 내장된 고속 FPGA(Field Programmable Gate Array)에서 효율적으로 구현할 수 있는 정수 나눗셈 알고리즘을 제안하였다. 제안된 알고리즘은 메모리를 이용한 Look-up Table(LUT)과 곱셈기를 사용하여 반복 계산(Iteration)구조로 FPGA의 자원을 최소화할 수 있으며 반복연산 횟수가 일반적으로 알려진 뺄셈 또는 뺄셈-곱셈에 의한 나눗셈 알고리즘에 비해 매우 적어 Latency를 최소화 할 수 있다. Xilinx사의 Virtex-4 FPGA에 VHDL coding을 통해 Pipeline구조로 구현한 결과 17bit의 정수 나눗셈을 300MSPS( Mega Sample per Second)의 속도로 수행하였다. 또한 일반적으로 사용되고 있는 뺄셈 또는 뺄셈-곱셈 구조에 비해 FPGA의 소요자원인 Slices의 경우 1/6이하, 곱셈기-누산기 수는 1/4이하로 줄일 수 있었으며, 입출력 간의 지연 Latency를 1/3이하로 줄일 수 있어 다른 알고리즘에 비해 매우 효율적인 구조임을 확인하였다.