• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.5
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• pp.674-680
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• 1986

In this paper, a new design method for high density PLA by a simple row folding technique is proposed. The normal input line and its complement line of different two input lines are folded on the same row. Especially the only one input line pair of the different two input lines are folded by this method. Conseqently, the results of folding are better than those of conventional methods. An efficient technique of ordering columns is described. Also, constraints about outside circuitry are consideted in this algorithm. The proposed algorithm has been implemented on a personal computer by C language.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.82-90
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• 2002

BDD have become widely used for various CAD applications because Boolean functions can be represented uniquely and compactly by using BDD. The size of the BDD representation for a function is very sensitive to the choice of orderings on the input variable. Therefore, it is very important to find a good variable ordering which minimize the size of the BDD. Since finding an optimal ordering is NP-complete, several heuristic algorithms have been proposed to find good variable orderings. In this paper, we propose a variable ordering algorithm, Faster-${\mu}$0, based on the ${\mu}$0(microcanonical optimization). In the Faster-${\mu}$0 algorithm, the initialization phase is replaced with a shifting phase to produce better solutions in a fast local search. We find values for algorithm parameters experimentally and the proposed algorithm has been experimented on well known benchmark circuits and shows superior performance compared to various existing algorithms.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.635-641
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• 2010

Time-varying channel characteristics in OFDM systems over doubly selective channels cause inter-carrier interferences(ICI) in the frequency domain. Time domain windowing gives rise to restriction on the bandwidth of the frequency domain channel matrix and makes it possible to approximate the OFDM system as a simplified linear input-output model. When successive interference cancellation based on linear MMSE estimation is employed for channel equalization in OFDM systems, symbol detection ordering produces considerable effects on overall system performances. In this paper, we show the reduction of the residual ICI by time domain windowing and the resultant performance improvements, and investigate the effects of SINR- and CSEP-based symbol detection ordering on the performance of successive interference cancellation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.6C
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• pp.560-569
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• 2005

This paper proposes an algorithm for transmit antenna selection in a multi-input multi-output(MIMO) spatial multiplexing system with per antenna rate control(PARC) and an ordered successive interference cancellation (OSIC) receiver. The active antenna subset is determined at the receiver and conveyed to the transmitter using feedback information on transmission rate per antenna. We propose a serial decision procedure consisting of a successive process that tests whether antenna selection gain exists when the antenna with the lowest pre-processing signal to interference and noise ratio(SINR) is discarded at each stage. Furthermore, we show that 'reverse detection ordering', whereby the signal with the lowest SINR is decoded at each stage of successive decoding, widens the disparities among fractions of the whole capacity allocated to each individual antenna and thus maximizes a gain of antenna selection. Numerical results show that the proposed reverse detection ordering based serial antenna selection approaches the closed-loop MIMO capacity and that it induces a negligible capacity loss compared with the heuristic selection strategy even with considerably reduced complexity.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.252-256
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• 2006

A low-power ECC check bit generator is presented with competent DRAM implementation with minimal speed loss, area overhead and power consumption. The ECC used in the proposed scheme is a variant form of the minimum weight column code. The spatial and temporal correlations of input data are analyzed and the input paths of the check bit generator are ordered for the on-line adaptable power savings up to 24.4% in the benchmarked cases. The chip size overhead is estimated to be under 0.3% for a 80nm 1Gb DRAM implementation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.523-529
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• 2017

In this paper, we propose an efficient sphere decoding scheme that reduces computational complexity by combining receive and transmit ordering techniques in generalized spatial modulation systems, where the indexes of activated transmit antennas as well as the transmit symbols are exploited to transfer information to the receiver. In this scheme, the receive signals are optimally ordered so that the calculation for a candidate solution outside the sphere is terminated early to lower the computational complexity. In addition, the transmit ordering technique is applied to first search for candidate symbols and activated antennas having higher probabilities to further reduce the computational complexity. Simulation results show that the proposed doubly ordered sphere decoding scheme provides the same bit error rate performance with the conventional sphere decoding method and the sphere decoder employing only the receive ordering technique while it requires lower computational complexity.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.1-12
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• 1999

A new algorithm of constructing binary decision diagram(BDD) for design verification of switch-level circuits is proposed in this paper. In the switch-level circuit, functions are characterized by serial and parallel connections of switches and the final logic values may have high-impedance and unstable states in addition to the logic values of 0 and 1. We extend the BDD to represent functions of switch-level circuits as acyclic graphs so called switch-level binary decision diagram (SLBDD). The function representation of the graph is in the worst case, exponential to the number of inputs. Thus, the ordering of decision variables plays a major role in graph sizes. Under the existence of pass-transistors and domino-logic of precharging circuitry, we also propose an input ordering algorithm for the efficiency in graph sizes. We conducted several experiments on various benchmark circuits and the results show that our algorithm is efficient enough to apply to functional simulation, power estimation, and fault-simulation of switch-level design.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.6
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• pp.35-46
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• 2007

This paper proposes a six-color separation method of reducing unnecessary usage of colorants based on the limitation of total colorant amount and dot visibility ordering. First, the CIELAB values of input RGB image are estimated through the color-mixing model and compared with pre-calculated CIELAB values corresponding to all combination of CMYKlclm colorants with a constraint of color difference, thereby selecting initial CMYKlclm candidates. Next, the limitation on total colorant amount Is imposed on initial CMYKlclm candidates to remove the excessive amounts of colorants, and then final CMYKlclm candidates are determined by minimizing the usage of light cyan and light magenta in the dark region based on the dot visibility ordering of C, M, Y, K, lc, and lm. Through the experiment, the proposed method is shown to reduce the excessive amount of colorants with preserving good image quality.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12C
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• pp.1044-1051
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• 2010

In this paper, we propose an efficient soft-output signal detection method for spatially multiplexed multiple input multiple output (MIMO) systems. The proposed method is based on the ordered successive interference cancellation (OSIC) algorithm, but it significantly improves the performance of the original OSIC algorithm by solving the error propagation problem. The proposed method combines this enhanced OSIC (ESIC) algorithm with a multiple ordering technique in a very efficient way. As a result, the log likelihood ratio (LLR) values can be computed by using a very small set of candidate symbol vectors. The proposed method has been implemented with a $0.13{\mu}m$ CMOS technology for a $4{\times}4$ 16-QAM MIMO system. The simulation and implementation results show that the proposed detector provides a very good solution in terms of performance and hardware complexity.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.4
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• pp.440-448
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• 2019

In this paper, we propose an ordering chatbot that can process multiple keywords based on recursive slot-filling method. In general, in case of an order service using chatbots, the whole order process is performed only according to the sequence defined by the developer. That is, among all the information needed for the whole order process, only one input can be processed at one time. In order to reduce processing step for the order, we propose a recursive slot-filling method which fills out multiple slots per one time by extracting multiple keywords. First, a keyword array for the order is created according to the order related information. Next, from the input sentence of a user, multiple keywords is extracted. Corresponding slots for a keyword array will be filled with the extracted keywords. Finally, recursive routine will be executed to fill out all the blank in the keyword array. The usability and validity of the proposed method will be shown from the implementation of a smartphone application.