• Title/Summary/Keyword: input delay

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A Study on the Accurate Stopping Control of a Train for the Urban Rail Transit Using Kalman Filter (칼만 필터를 이용한 도시철도 열차 정위치 정차에 관한 연구)

  • Kim, Jungtai;Lee, Jaeho;Kim, Moo Sun;Park, Chul Hong
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.11
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    • pp.655-662
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    • 2016
  • Accurate stopping control is important for trains, especially now that many train stations are equipped with platform screen doors. Various algorithms have been proposed for accurate stopping control. However, most metro trains in South Korea use classic control algorithms such as PID control because other algorithms are too complex to realize. PID control has merits of simple structure and operation. However, PID control sometimes fails, and much time is needed to find the proper coefficients due to the long control period and the brake delay. We propose a control algorithm that uses a Kalman filter. The Kalman filter estimates the states at the time when braking starts. Then, a suitable control input is derived for proper control. System modeling and a computer simulation were performed with consideration of the brake properties and the period of the control system. The superiority of the proposed control algorithm is shown by analyzing stop errors.

A Study on Development of A GPS navigation system based on RFID which contains location information (위치정보가 기록된 RFID를 이용한 택배차량용 내비게이션 시스템 개발에 관한 연구)

  • Shim, Jin-Bum;Han, Yeong-Geun
    • Journal of the Korea Safety Management & Science
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    • v.12 no.1
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    • pp.113-118
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    • 2010
  • "Domestic delivery service" is defined the service to deliver goods or packages from point of senders to point of receiver. With the characteristics of door to door, it is must a service provider should know the exact location of destination assuring best utilization of moving path. Generally, location information consist of postal code and address only, which result in difficulties to identify the precise location of destination. It is relatively less correlated between the information that address refers and practical location in Korea address system. For example, the next door to house number 100 is not always house number 101. Therefore, a delivery man additionally uses a paper map or a GPS navigation which carry extra job to input every code of location to the device in order to know precise location. It is also very inconvenient that every delivery man identify the location that address information refers and make a personal decision of the optimum moving path dropping each destination without calculating provisioning process of whole delivery path. As explained above, it is inefficient to find information delivery service required and to generate the optimum path. In results, these difficulties bring in delay of service and increase of cost. In this point, the contents of the thesis suggest a GPS navigation system easy to obtain accuracy of delivery information which enables to automate optimum moving path based on RFID which contains location information.

Performance Improvement and ASIC Design of OAM Function Using Special Cell Field (특별 셀 영역을 이용한 OAM 기능의 성능 향상 및 ASIC 설계)

  • Park, Hyoung-Keun;Kim, Hwan-Yong
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.2
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    • pp.26-36
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    • 1999
  • In this paper, the novel scheme of OAM performance management function is proposed to supply the most of network resources and reliable services by processing data having various QoS(quality of service) in the view of cell loss and cell delay of ATM networks Also, the special fields of OAM cell are defined in order to improve correlate control, operation, and management technique between networks which is required to flexibility and precision control as detecting the performance information of the variable networks periodically. The proposed OAM function, the input/output function of cell, and the interface function of the accessory device which is likely to the memory/CPU are designed to ASIC. The designed chip is carried out the back-end simulation using Verilog-XL simulator of Cadence. In result, it is able to performs an accurate control in $2{\mu}s$.

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Position Synchronization Control of Single Link Manipulators (단일 링크 머니퓰레이터들에 대한 위치 동기화 제어)

  • Song, Ki-Won
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.48 no.3
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    • pp.6-12
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    • 2011
  • Electric vehicles and robots are real-time distributed control systems composed of multiple drive subsystems using micro controller units. Each control subsystem should be modular, compact, power saving, interoperable and fault tolerable in order to be incorporated into the networked real-time distributed control system. Under the networked real-time distributed control the synchronization problem can be occurred to the position and orientation tracking control due to the load variance, mismatch and time delay between the multiple drive subsystems. This paper suggests two types of position synchronization control of the single link manipulators. One of them is composed of cross controller, Kalman filter and disturbance observer, and the other uses the generation of target trajectories to minimize the gradient vector of the scalar function which is composed of the sum of square errors between the reference input vector and the output vectors. The availability of the proposed control schemes is shown through the control experiments.

Temporal characterization of femtosecond laser pulses using spectral phase interferometry for direct electric-field reconstuction (주파수 위상 간섭계를 이용한 펨토초 레이저 펄스의 시간적 특성연구)

  • 강용훈;홍경한;남창희
    • Korean Journal of Optics and Photonics
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    • v.12 no.3
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    • pp.219-224
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    • 2001
  • Spectral phase interferometry for direct electric-field reconstruction (SPIDER) was fabricated and used to characterize pulses from a Ti:sapphire oscillator. In the SPIDER apparatus, two replicas of the input pulse were generated with a time delay of 200 fs and were upconverted by use of sum-frequency generation with a strongly chirped pulse using a 8-cm-long SFIO glass block at a 30-11m-thick type II BBO (p-BaBz04) crystal. The resulting interferogram was recorded with a UV-enhanced CCD array in the spectrometer. The spectral phase was retrieved by SPIDER algorithm in combination with independently measured pulse spectrum and the corresponding temporal intensity profile was reconstructed with a duration of 19 fs. As an independent cross-check of the accuracy of the method, we compared the interferometric autocorrelation (lAC) signal calculated from the SPIDER data with a separately measured lAC. The conventional, but unjustified, method of fitting a sechz pulse to the autocorrelation deceivingly yielded a pulse duration of 15 fs. This systematic underestimation of the pulse duration affirms the need for a complete characterization method. From the consideration in this paper, we concluded that the SPIDER could provide an accurate characterization of femtosecond pulses. ulses.

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Fingertip Detection through Atrous Convolution and Grad-CAM (Atrous Convolution과 Grad-CAM을 통한 손 끝 탐지)

  • Noh, Dae-Cheol;Kim, Tae-Young
    • Journal of the Korea Computer Graphics Society
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    • v.25 no.5
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    • pp.11-20
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    • 2019
  • With the development of deep learning technology, research is being actively carried out on user-friendly interfaces that are suitable for use in virtual reality or augmented reality applications. To support the interface using the user's hands, this paper proposes a deep learning-based fingertip detection method to enable the tracking of fingertip coordinates to select virtual objects, or to write or draw in the air. After cutting the approximate part of the corresponding fingertip object from the input image with the Grad-CAM, and perform the convolution neural network with Atrous Convolution for the cut image to detect fingertip location. This method is simpler and easier to implement than existing object detection algorithms without requiring a pre-processing for annotating objects. To verify this method we implemented an air writing application and showed that the recognition rate of 81% and the speed of 76 ms were able to write smoothly without delay in the air, making it possible to utilize the application in real time.

Implementation of a LSB-First Digit-Serial Multiplier for Finite Fields GF(2m) (유한 필드 GF(2m)상에서의 LSB 우선 디지트 시리얼 곱셈기 구현)

  • Kim, Chang-Hun;Hong, Chun-Pyo;U, Jong-Jeong
    • The KIPS Transactions:PartA
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    • v.9A no.3
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    • pp.281-286
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    • 2002
  • In this paper we, implement LSB-first digit-serial systolic multiplier for computing modular multiplication $A({\times})B$mod G ({\times})in finite fields GF $(2^m)$. If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of regularity, modularity, and unidirectional data flow, it shows good extension characteristics with respect to m and L.

Definition of Performance Indices and Unplementation of Tester for SIP Servers in Next Generation Networks (차세대 방 SIP 서버 시험을 위한 성능 지표 및 시험기 구현)

  • 김용권;박준형;기장근;이규호;최길영;최진규
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.4B
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    • pp.411-423
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    • 2004
  • This paper defines test methodologies and performance indices for SIP server system, and describes elements that can have influence on the test of SIP network equipments. Moreover, we implement a tester to evaluate the performance of SIP Servers such as Registrar and Proxy server. The performance indices for testing SIP servers are message processing rate, transaction delay, and call success probability. The parameters that can have an effect on the performance of SIP servers are user population, transport protocol, method of database access, method of DNS, call creation pattern, definition of transactions, and size of packets. We tested several SIP servers that act as Registrar, Proxy, and Redirect server using the implemented SIP tester, and, as a result, verified functions of the tester and performance indices and input parameters defined in this paper. Performance indices and methodologies presented in this paper can be used to evaluate SIP servers in NGN

VLSI Design of a 2048 Point FFT/IFFT by Sequential Data Processing for Digital Audio Broadcasting System (순차적 데이터 처리방식을 이용한 디지틀 오디오 방송용 2048 Point FFT/IFFT의 VLSI 설계)

  • Choe, Jun-Rim
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.5
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    • pp.65-73
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    • 2002
  • In this paper, we propose and verify an implementation method for a single-chip 2048 complex point FFT/IFFT in terms of sequential data processing. For the sequential processing of 2048 complex data, buffers to store the input data are necessary. Therefore, DRAM-like pipelined commutator architecture is used as a buffer. The proposed structure brings about the 60% chip size reduction compared with conventional approach by using this design method. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of the cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding and their method contributed to a single chip design of digital audio broadcasting system.

Design of a Low Power High Speed Conditional Select Adder/Subtracter for Next Generation ASIC Library (차세대 ASIC 라이브러리를 위한 고속 저전력 조건 선택 덧셈기/뺄셈기의 설계)

  • Cho, Ki-Seon;Song, Min-Kyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.11
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    • pp.59-66
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    • 2000
  • As multimedia applications become popular, computers increasingly require high-speed DSP for 3-DIM computer graphic. In this Paper, a Macro-cell Library of conditional select adder/subtracter is proposed for DSP within high speed and low power consumption. Using, this design method, we are able to obtain an auto generation of the adder or(and) subtracter from 8-bit to 64-bit. The proposed adder/subtracter has been fabricated with a 0.25${\mu}m$, single-poly, five-metal, N-well CMOS technology. From the experimental results, delay time is 3.43ns, and the power consumption is 42.8${\mu}w$/MHz at the input frequency of 50MHz, at 2.5V single power supply, in case of the 32-bit adder/subtracter.

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