• Title/Summary/Keyword: information transfer complexity

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Design of QDI Model Based Encoder/Decoder Circuits for Low Delay-Power Product Data Transfers in GALS Systems (GALS 시스템에서의 저비용 데이터 전송을 위한 QDI모델 기반 인코더/디코더 회로 설계)

  • Oh Myeong-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.1 s.343
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    • pp.27-36
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    • 2006
  • Conventional delay-insensitive (DI) data encodings usually require 2N+1 wires for transferring N-bit. To reduce complexity and power dissipation of wires in designing a large scaled chip, an encoder and a decoder circuits, where N-bit data transfer can be peformed with only N+l wires, are proposed. These circuits are based on a quasi delay-insensitive (QDI) model and designed by using current-mode multiple valued logic (CMMVL). The effectiveness of the proposed data transfer mechanism is validated by comparisons with conventional data transfer mechanisms using dual-rail and 1-of-4 encodings through simulation at the 0.25 um CMOS technology. In general, simulation results with wire lengths of 4 mm or larger show that the CMMVL scheme significantly reduces delay-power product ($D{\ast}P$) values of the dual-rail encoding with data rate of 5 MHz or more and the 1-of-4 encoding with data rate of 18 MHz or more. In addition, simulation results using the buffer-inserted dual-rail and 1-of-4 encodings for high performance with the wire length of 10 mm and 32-bit data demonstrate that the proposed CMMVL scheme reduces the D*P values of the dual-rail encoding with data rate of 4 MHz or more and 1-of-4 encoding with data rate of 25 MHz or more by up to $57.7\%\;and\;17.9\%,$ respectively.

A Study on Automatic Generation of Interface Circuits Based on FSM between Standard Buses and Ips (FSM을 이용한 표준화된 버스와 IP간의 인터페이스 회로 자동생성에 관한 연구)

  • Lee, Ser-Hoon;Moon, Jong-Uk;Hwang, Sun-Young
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.2A
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    • pp.137-146
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    • 2005
  • IP-based design methodology has been popularly employed for SoC design to reduce design complexity and to cope with time-to-market pressure. Interface modules for communication between system buses and IPs are required, since many IPs employ different protocols. Automatic generation of these interface modules would enhance designer's productivity and IP's reusability. This paper proposes an automatic interface generation system based on FSM generated from the protocol description of IPs. The proposed system provides the library modules for the standard buses to reduce the burdens of describing the protocols for data transfer from/to standard buses. Experimental results show that the area of the interface circuits generated by the proposed system had been increased slightly by 4.5% on the average when compared to manual designs. In the experiment, where bus clock is 100 Mhz and slave module clock is 34 Mhz, the latency of the interface had been increased by 7.1% in burst mode to transfer 16 data words. However, occupation of system bus can be reduce by 64.9%. A chip designer can generate an interface that improves the efficiency of system bus, by using this system.

A Multipurpose Design Framework for Hardware-Software Cosimulation of System-on-Chip (시스템-온-칩의 하드웨어-소프트웨어 통합 시뮬레이션을 위한 다목적 설계 프레임워크)

  • Joo, Young-Pyo;Yun, Duk-Young;Kim, Sung-Chan;Ha, Soon-Hoi
    • Journal of KIISE:Computer Systems and Theory
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    • v.35 no.9_10
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    • pp.485-496
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    • 2008
  • As the complexity of SoC (System-on-Chip) design increases dramatically. traditional system performance analysis and verification methods based on RTL (Register Transfer Level) are no more valid for increasing time-to-market pressure. Therefore a new design methodology is desperately required for system verification in early design stages. and hardware software (HW-SW) cosimulation at TLM (Transaction Level Modeling) level has been researched widely for solving this problem. However, most of HW-SW cosimulators support few restricted ion levels only, which makes it difficult to integrate HW-SW cosimulators with different ion levels. To overcome this difficulty, this paper proposes a multipurpose framework for HW SW cosimulation to provide systematic SoC design flow starting from software application design. It supports various design techniques flexibly for each design step, and various HW-SW cosimulators. Since a platform design is possible independently of ion levels and description languages, it allows us to generate simulation models with various ion levels. We verified the proposed framework to model a commercial SoC platform based on an ARM9 processor. It was also proved that this framework could be used for the performance optimization of an MJPEG example up to 44% successfully.

Biological Inspiration toward Artificial Photostystem

  • Park, Jimin;Lee, Jung-Ho;Park, Yong-Sun;Jin, Kyoungsuk;Nam, Ki Tae
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.08a
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    • pp.91-91
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    • 2013
  • Imagine a world where we could biomanufacture hybrid nanomaterials having atomic-scale resolution over functionality and architecture. Toward this vision, a fundamental challenge in materials science is how to design and synthesize protein-like material that can be fully self-assembled and exhibit information-specific process. In an ongoing effort to extend the fundamental understanding of protein structure to non-natural systems, we have designed a class of short peptides to fold like proteins and assemble into defined nanostructures. In this talk, I will talk about new strategies to drive the self-assembled structures designing sequence of peptide. I will also discuss about the specific interaction between proteins and inorganics that can be used for the development of new hybrid solar energy devices. Splitting water into hydrogen and oxygen is one of the promising pathways for solar to energy convertsion and storage system. The oxygen evolution reaction (OER) has been regarded as a major bottleneck in the overall water splitting process due to the slow transfer rate of four electrons and the high activation energy barrier for O-O bond formation. In nature, there is a water oxidation complex (WOC) in photosystem II (PSII) comprised of the earthabundant elements Mn and Ca. The WOC in photosystem II, in the form of a cubical CaMn4O5 cluster, efficiently catalyzes water oxidation under neutral conditions with extremely low overpotential (~160 mV) and a high TOF number. The cluster is stabilized by a surrounding redox-active peptide ligand, and undergo successive changes in oxidation state by PCET (proton-coupled electron transfer) reaction with the peptide ligand. It is fundamental challenge to achieve a level of structural complexity and functionality that rivals that seen in the cubane Mn4CaO5 cluster and surrounding peptide in nature. In this presentation, I will present a new strategy to mimic the natural photosystem. The approach is based on the atomically defined assembly based on the short redox-active peptide sequences. Additionally, I will show a newly identified manganese based compound that is very close to manganese clusters in photosystem II.

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Design and Implementation of a Virtual MCU Based on SystemC to Provide the Implementation Environment of MAC Layer Software (MAC 계층 소프트웨어의 구현 환경을 제공하기 위한 SystemC 기반의 가상 MCU 모듈의 설계 및 구현)

  • Jeong, Yoo-Jin;Park, Soo-Jin;Lee, Ho-Eung;Park, Hyun-Ju
    • Journal of Internet Computing and Services
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    • v.10 no.6
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    • pp.7-17
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    • 2009
  • The development of wireless communication MAC layer is usually released as SoC which is a combination in hardware and software. In this system development environment, an environment for software development and verification is necessary because the hardware development takes a lot of time priori to completion. In integrated development of hardware and software, simulation environment of hardware and software provided by hardware modeling using HDL at RTL and ISS respectively. By increasing the development complexity of system, ESL design modeling systems at higher abstraction level than RTL has already prompted. The ESL design is divided untime model and time model. This paper present design and implementation of MCU for untime model simulation, not time model. Proposed MCU can optimize the system at early step of system development and move up the development completion time by verifying the system function easily and rapidly than part required exact time in untime model. In this paper, we present an MCU module based on SystemC and UC/OS-II Module providing real-time operate system.

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Design of Low-complexity FFT Processor for Multi-mode Radar Signal Processing (멀티모드 레이다 신호처리를 위한 저복잡도 FFT 프로세서 설계)

  • Park, Yerim;Jung, Yongchul;Jung, Yunho
    • Journal of Advanced Navigation Technology
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    • v.24 no.2
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    • pp.85-91
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    • 2020
  • Recently, a multi-mode radar system was designed for efficient operation of unmanned aerial vehicles (UAVs) in various environments, which has the advantage of being able to integrate and utilize methods of the pulse Doppler (PD) radar and the frequency modulated continuous wave (FMCW) radar. For the range detection part of the multi-mode radar signal processor (RSP), the hardware structure using the FFT processor and the IFFT processor is required to be designed in a way that improves efficiency on the area side. In addition, given the radar application environment that requires a variety of distance resolutions, FFT processors need to support variable-length operations. In this paper, the FFT processor and IFFT processor in multi-mode RSP range estimation are designed and proposed as hardware for a single FFT processor that supports variable length operation of 16-1024 points. The proposed FFT processor designed in hardware description language (HDL) and can be implemented with 7,452 logic elements and 5,116 registers.

Blind Adaptive Equalization of Partial Response Channels (부분 응답 채널에서의 블라인드 적응 등화 기술에 관한 연구)

  • 이상경;이재천
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.26 no.11A
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    • pp.1827-1840
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    • 2001
  • In digital data transmission/storage systems, the compensation for channel distortion is conducted normally using a training sequence that is known a priori to both the sender and receiver. The use of the training sequences results in inefficient utilization of channel bandwidth. Sometimes, it is also impossible to send training sequences such as in the burst-mode communication. As such, a great deal of attention has been given to the approach requiring no training sequences, which has been called the blind equalization technique. On the other hand, to utilize the limited bandwidth effectively, the concept of partial response (PR) signaling has widely been adopted in both the high-speed transmission and high-density recording/playback systems such as digital microwave, digital subscriber loops, hard disk drives, digital VCRs and digital versatile recordable disks and so on. This paper is concerned with blind adaptive equalization of partial response channels whose transfer function zeros are located on the unit circle, thereby causing some problems in performance. Specifically we study how the problems of blind channel equalization associated with the PR channels can be improved. In doing so, we first discuss the existing methods and then propose new structures for blind PR channel equalization. Our structures have been extensively tested by computer simulation and found out to be encouraging in performance. The results seem very promising as well in terms of the implementation complexity compared to the previous approach reported in literature.

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Transfer Learning using Multiple ConvNet Layers Activation Features with Principal Component Analysis for Image Classification (전이학습 기반 다중 컨볼류션 신경망 레이어의 활성화 특징과 주성분 분석을 이용한 이미지 분류 방법)

  • Byambajav, Batkhuu;Alikhanov, Jumabek;Fang, Yang;Ko, Seunghyun;Jo, Geun Sik
    • Journal of Intelligence and Information Systems
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    • v.24 no.1
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    • pp.205-225
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    • 2018
  • Convolutional Neural Network (ConvNet) is one class of the powerful Deep Neural Network that can analyze and learn hierarchies of visual features. Originally, first neural network (Neocognitron) was introduced in the 80s. At that time, the neural network was not broadly used in both industry and academic field by cause of large-scale dataset shortage and low computational power. However, after a few decades later in 2012, Krizhevsky made a breakthrough on ILSVRC-12 visual recognition competition using Convolutional Neural Network. That breakthrough revived people interest in the neural network. The success of Convolutional Neural Network is achieved with two main factors. First of them is the emergence of advanced hardware (GPUs) for sufficient parallel computation. Second is the availability of large-scale datasets such as ImageNet (ILSVRC) dataset for training. Unfortunately, many new domains are bottlenecked by these factors. For most domains, it is difficult and requires lots of effort to gather large-scale dataset to train a ConvNet. Moreover, even if we have a large-scale dataset, training ConvNet from scratch is required expensive resource and time-consuming. These two obstacles can be solved by using transfer learning. Transfer learning is a method for transferring the knowledge from a source domain to new domain. There are two major Transfer learning cases. First one is ConvNet as fixed feature extractor, and the second one is Fine-tune the ConvNet on a new dataset. In the first case, using pre-trained ConvNet (such as on ImageNet) to compute feed-forward activations of the image into the ConvNet and extract activation features from specific layers. In the second case, replacing and retraining the ConvNet classifier on the new dataset, then fine-tune the weights of the pre-trained network with the backpropagation. In this paper, we focus on using multiple ConvNet layers as a fixed feature extractor only. However, applying features with high dimensional complexity that is directly extracted from multiple ConvNet layers is still a challenging problem. We observe that features extracted from multiple ConvNet layers address the different characteristics of the image which means better representation could be obtained by finding the optimal combination of multiple ConvNet layers. Based on that observation, we propose to employ multiple ConvNet layer representations for transfer learning instead of a single ConvNet layer representation. Overall, our primary pipeline has three steps. Firstly, images from target task are given as input to ConvNet, then that image will be feed-forwarded into pre-trained AlexNet, and the activation features from three fully connected convolutional layers are extracted. Secondly, activation features of three ConvNet layers are concatenated to obtain multiple ConvNet layers representation because it will gain more information about an image. When three fully connected layer features concatenated, the occurring image representation would have 9192 (4096+4096+1000) dimension features. However, features extracted from multiple ConvNet layers are redundant and noisy since they are extracted from the same ConvNet. Thus, a third step, we will use Principal Component Analysis (PCA) to select salient features before the training phase. When salient features are obtained, the classifier can classify image more accurately, and the performance of transfer learning can be improved. To evaluate proposed method, experiments are conducted in three standard datasets (Caltech-256, VOC07, and SUN397) to compare multiple ConvNet layer representations against single ConvNet layer representation by using PCA for feature selection and dimension reduction. Our experiments demonstrated the importance of feature selection for multiple ConvNet layer representation. Moreover, our proposed approach achieved 75.6% accuracy compared to 73.9% accuracy achieved by FC7 layer on the Caltech-256 dataset, 73.1% accuracy compared to 69.2% accuracy achieved by FC8 layer on the VOC07 dataset, 52.2% accuracy compared to 48.7% accuracy achieved by FC7 layer on the SUN397 dataset. We also showed that our proposed approach achieved superior performance, 2.8%, 2.1% and 3.1% accuracy improvement on Caltech-256, VOC07, and SUN397 dataset respectively compare to existing work.

Concepts of Disaster Prevention Design for Safety in the Future Society

  • Noh, Hwang-Woo;Kitagawa, Keiko;Oh, Yong-Sun
    • International Journal of Contents
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    • v.10 no.1
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    • pp.54-61
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    • 2014
  • In this paper, we propose a pioneering concept of DPD(Disaster Prevention Design) to realize a securable society in the future. Features of danger in the future society are expected to be diverse, abrupt occurring, large scale, and complicated ways. Due to increment of dangers with their features of uncertainty, interactivity, complexity, and accumulation, human-oriented design concept naturally participates in activities to prevent our society against disasters effectively. We presented DPD is an essential design activity in order to cope with dangers expected in the future societies as well as realize securable environments. DPD is also an integrated design aids including preemptive protections, rapid preparing, recovery, and interactive cooperation. We also expect these activities of DPD is effective for generation of new values in the market, satisfaction of social needs, expansion of design industry, and a novel chance for development in the future society. Throughout this paper, we submit various aspects of DPD concepts including definition, classification, scope, necessity, strategy, influencing elements, process, and its principle. We expect these concepts will be the seed and/or basement of DPD research for the future works. For the direction of study for DPD in the future, we emphasize alarm system for preemptive protection rather than recovery strategy for the damage occurred. We also need to research about progressive prevention techniques and convergence with other areas of design. In order to transfer the concept of product design from facility-oriented mechanism to human-oriented one, we should develop new kinds of city basis facilities, public-sense design concepts referred to social weak-party, e-Learning content design preparing disasters, and virtual simulation design etc. On the other hand, we have to establish laws and regulations to force central and/or provincial governments to have these DPD strategies applying their regional properties. Modern design activities are expanding to UI(user interface) content design area overcoming the conventional design concept of product and/or service. In addition, designers are recognized as art directors or life stylists who will change the human life and create the social value. DPD can be divided into prevention design, preparedness design, response design, and recovery design. Five strategies for successful DPD are Precaution-oriented, Human-oriented, Sense-oriented, Legislation, and Environment Friendly Strategies.

An I/O Interface Circuit Using CTR Code to Reduce Number of I/O Pins (CTR 코드를 사용한 I/O 핀 수를 감소 시킬 수 있는 인터페이스 회로)

  • Kim, Jun-Bae;Kwon, Oh-Kyong
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.36D no.1
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    • pp.47-56
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    • 1999
  • As the density of logic gates of VLSI chips has rapidly increased, more number of I/O pins has been required. This results in bigger package size and higher packager cost. The package cost is higher than the cost of bare chips for high I/O count VLSI chips. As the density of logic gates increases, the reduction method of the number of I/O pins for a given complexity of logic gates is required. In this paper, we propose the novel I/O interface circuit using CTR (Constant-Transition-Rate) code to reduce 50% of the number of I/O pins. The rising and falling edges of the symbol pulse of CTR codes contain 2-bit digital data, respectively. Since each symbol of the proposed CTR codes contains 4-bit digital data, the symbol rate can be reduced by the factor of 2 compared with the conventional I/O interface circuit. Also, the simultaneous switching noise(SSN) can be reduced because the transition rate is constant and the transition point of the symbols is widely distributed. The channel encoder is implemented only logic circuits and the circuit of the channel decoder is designed using the over-sampling method. The proper operation of the designed I/O interface circuit was verified using. HSPICE simulation with 0.6 m CMOS SPICE parameters. The simulation results indicate that the data transmission rate of the proposed circuit using 0.6 m CMOS technology is more than 200 Mbps/pin. We implemented the proposed circuit using Altera's FPGA and confimed the operation with the data transfer rate of 22.5 Mbps/pin.

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