• Title/Summary/Keyword: inductive peaking

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A 6 Gb/s Low Power Transimpedance Amplifier with Inductor Peaking and Gain Control for 4-channel Passive Optical Network in 0.13 μm CMOS

  • Lee, Juri;Park, Hyung Gu;Kim, In Seong;Pu, YoungGun;Hwang, Keum Cheol;Yang, Youngoo;Lee, Kang-Yoon;Seo, Munkyo
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.1
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    • pp.122-130
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    • 2015
  • This paper presents a 6 Gb/s 4-channel arrayed transimpedance amplifiers (TIA) with the gain control for 4-channel passive optical network in $0.13{\mu}m$ complementary metal oxide semiconductor (CMOS) technology. A regulated cascode input stage and inductive-series peaking are proposed in order to increase the bandwidth. Also, a variable gain control is implemented to provide flexibility to the overall system. The TIA has a maximum $98.1dB{\Omega}$ gain and an input current noise level of about 37.8 pA/Hz. The die area of the fabricated TIA is $1.9mm{\times}2.2mm$ for 4-channel. The power dissipation is 47.64 mW/1ch.

Highly Linear Wideband LNA Design Using Inductive Shunt Feedback

  • Jeong, Nam Hwi;Cho, Choon Sik;Min, Seungwook
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.1
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    • pp.100-108
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    • 2014
  • Low noise amplifier (LNA) is an integral component of RF receiver and frequently required to operate at wide frequency bands for various wireless system applications. For wideband operation, important performance metrics such as voltage gain, return loss, noise figure and linearity have been carefully investigated and characterized for the proposed LNA. An inductive shunt feedback configuration is successfully employed in the input stage of the proposed LNA which incorporates cascaded networks with a peaking inductor in the buffer stage. Design equations for obtaining low and high impedance-matching frequencies are easily derived, leading to a relatively simple method for circuit implementation. Careful theoretical analysis explains that input impedance can be described in the form of second-order frequency response, where poles and zeros are characterized and utilized for realizing the wideband response. Linearity is significantly improved because the inductor located between the gate and the drain decreases the third-order harmonics at the output. Fabricated in $0.18{\mu}m$ CMOS process, the chip area of this wideband LNA is $0.202mm^2$, including pads. Measurement results illustrate that the input return loss shows less than -7 dB, voltage gain greater than 8 dB, and a little high noise figure around 6-8 dB over 1.5 - 13 GHz. In addition, good linearity (IIP3) of 2.5 dBm is achieved at 8 GHz and 14 mA of current is consumed from a 1.8 V supply.

An Wideband GaN Low Noise Amplifier in a 3×3 mm2 Quad Flat Non-leaded Package

  • Park, Hyun-Woo;Ham, Sun-Jun;Lai, Ngoc-Duy-Hien;Kim, Nam-Yoon;Kim, Chang-Woo;Yoon, Sang-Woong
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.2
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    • pp.301-306
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    • 2015
  • An ultra-compact and wideband low noise amplifier (LNA) in a quad flat non-leaded (QFN) package is presented. The LNA monolithic microwave integrated circuit (MMIC) is implemented in a $0.25{\mu}m$ GaN IC technology on a Silicon Carbide (SiC) substrate provided by Triquint. A source degeneration inductor and a gate inductor are used to obtain the noise and input matching simultaneously. The resistive feedback and inductor peaking techniques are employed to achieve a wideband characteristic. The LNA chip is mounted in the $3{\times}3-mm^2$ QFN package and measured. The supply voltages for the first and second stages are 14 V and 7 V, respectively, and the total current is 70 mA. The highest gain is 13.5 dB around the mid-band, and -3 dB frequencies are observed at 0.7 and 12 GHz. Input and output return losses ($S_{11}$ and $S_{22}$) of less than -10 dB measure from 1 to 12 GHz; there is an absolute bandwidth of 11 GHz and a fractional bandwidth of 169%. Across the bandwidth, the noise figures (NFs) are between 3 and 5 dB, while the output-referred third-order intercept points (OIP3s) are between 26 and 28 dBm. The overall chip size with all bonding pads is $1.1{\times}0.9mm^2$. To the best of our knowledge, this LNA shows the best figure-of-merit (FoM) compared with other published GaN LNAs with the same gate length.

Design Optimization of Hybrid-Integrated 20-Gb/s Optical Receivers

  • Jung, Hyun-Yong;Youn, Jin-Sung;Choi, Woo-Young
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.4
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    • pp.443-450
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    • 2014
  • This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 $dB{\Omega}$ and 12 GHz, respectively. 20-Gb/s $2^{31}-1$ electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than $10^{-12}$. The receiver circuit has chip area of $0.5mm{\times}0.44mm$ and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.

Multichannel Transimpedance Amplifier Away in a $0.35\mu m$ CMOS Technology for Optical Communication Applications (광통신용 다채널 CMOS 차동 전치증폭기 어레이)

  • Heo Tae-Kwan;Cho Sang-Bock;Park Min Park
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.8 s.338
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    • pp.53-60
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    • 2005
  • Recently, sub-micron CMOS technologies have taken the place of III-V materials in a number of areas in integrated circuit designs, in particular even for the applications of gjgabit optical communication applications due to its low cost, high integration level, low power dissipation, and short turn-around time characteristics. In this paper, a four-channel transimpedance amplifier (TIA) array is realized in a standard 0.35mm CMOS technology Each channel includes an optical PIN photodiode and a TIA incorporating the fully differential regulated cascode (RGC) input configuration to achieve effectively enhanced transconductance(gm) and also exploiting the inductive peaking technique to extend the bandwidth. Post-layout simulations show that each TIA demonstrates the mid-band transimpedance gain of 59.3dBW, the -3dB bandwidth of 2.45GHz for 0.5pF photodiode capacitance, and the average noise current spectral density of 18.4pA/sqrt(Hz). The TIA array dissipates 92mw p in total from a single 3.3V supply The four-channel RGC TIA array is suitable for low-power, high-speed optical interconnect applications.

CMOS Transimpedance Amplifiers for Gigabit Ethernet Applications (기가비트 이더넷용 CMOS 전치증폭기 설계)

  • Park Sung-Min
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.4 s.346
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    • pp.16-22
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    • 2006
  • Gigabit transimpedance amplifiers are realihzed in submicron CMOS technologies for Gigabit Ethernet applications. The regulated cascode technique is exploited to enhance the bandwidth and noise performance simultaneously so that it can isolate the large input parasitic capacitance including photodiode capacitance from the determination of the bandwidth. The 1.25Gb/s TIA implemented in a 0.6um CMOS technology shows the measured results of 58dBohm transimpedance gain, 950MHz bandwidth for a 0.5pF photodiode capacitance, 6.3pA/sqrt(Hz) average noise current spectral density, and 85mW power dissipation from a single 5V supply. In addition, a 10Gb/s TIA is realized in a 0.18um CMOS incorporating the RGC input and the inductive peaking techniques. It provides 59.4dBohm transimpedance gain, 8GHz bandwidth for a 0.25pF photodiode capacitance, 20pA/sqrt(Hz) noise current spectral density, and 14mW power consumption for a single 1.8V supply.

Optimal Production of Protease from Entomopathogenic Fungus Beauveria bassiana (곤충 병원성 곰팡이 Beauveria bassiana로부터 Protease의 최적 생산)

  • Ko, Hwi-Jin;Kim, Hyun-Kyu;Kang, Sun-Chul;Kwon, Suk-Tae
    • Applied Biological Chemistry
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    • v.39 no.6
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    • pp.449-454
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    • 1996
  • We investigated the optimal condition for the production of extracellular pretense(a cuticle-degrading pretense) from entomopathogenic fungus Beauveria bassiana(ATCC7159) in liquid medium by adding of gelatin, bovine serum albumin(BSA), casein and polypeptone. The optimal induction medium for production of extracellular pretenses is composed of 0.5% polypeptone, trace elements and 50 mM potassium phosphate(pH 6.0). In this condition, the production of extracellular pretenses increased rapidly after the 24hrs, peaking at the third day and there was little inductive effect in culture broth more than pH 7.0. The pretenses were inhibited by phenyl methyl sulfonyl fluoride(PMSF). High activity of pretense was showed both range of pH 8.5 and 11.5 and also detected by three different portions of slice gel derived from non-denaturing isoelectricfocusing gel. At least three different extracellular pretenses are produced in optimal production medium when polypeptone is used as the sole carbon and nitrogen source.

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