• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
• /
• 2008.05a
• /
• pp.285-288
• /
• 2008

Even though many modular converters have several internal protection circuit blocks for various abnormal operation conditions, there are many failure cases on modular converters at real applications. In this paper, the control strategy for failure protection of converters with internal 'In-Hibit' function is investigated. As an example, for the MDl modular converters the in-hibit function application is realized and the test results shows that adopting in-hibit function while converter switching reduces the voltage and current stress. And the reduction of switching stress on converter will decrease failure rate on converters.

• 전기의세계
• /
• v.25 no.4
• /
• pp.68-72
• /
• 1976

This study is initiated to solve the problem that the development of an electric machine to drive heavy horse-power load required in the rural district, where only single phase supply is available, is very urgent. As a method for this purpose, the single/three phase converter by single phase induction machine with a tapped auxiliary winding, running unloaded mechanically under single-phase source and supplying three-phase output to a loaded 3-phase induction motor, is devised and the pilot machine is put into test. Analysis based on hybrid equivalent circuit for the phase converter and symmertical component theory for the 3-phase load motor and practical experiment result in that optimum auxiliary winding ratio is to be 1.25 rather than theoretical .root.3/2 in order to keep the voltage unbalance ratio of 3-phase output from the converter as low as possible in both cases of starting and running the load motor.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.22 no.5
• /
• pp.50-56
• /
• 1985

A common failure mechanism in bulk CMOS integrated circuits is the latch-up of parasitic SCR structure inherent in the bulk CMOS structure. Latch-up triggering and holding charac-teristics have been measured in the test devicrs which include conventional and Schottky-damped CMOS structures with various well depths and n+/p+ spacings. It is demonstrated that Schottky-clamped CMOS is more latch-up immune than conventional bulk CMOS. Finally, the simulation results by circuit simulation program (SPICE) are compared with measured results in order to verify the validity of the latch-up modal composed of nan, pnp transistors and two external resistors.

• Proceedings of the KIEE Conference
• /
• 1994.07b
• /
• pp.1543-1546
• /
• 1994

Ignitabilility of explosive gas mixture by spark of dry cell in case of short circuit by accident was studied for the purpose of evaluation of intrinsically safe characteristics of dry cell that manufactured in Korea. IEC type spark test apparatus, $21{\pm}2$ Vol% of hydrogen - air mixture, and dry cell that produced in Korea was used for the experiment. The result of this research could be used for design, manufacturing, and using the intrinsically safe electrical apparatus.

• Bulletin of the Korean Space Science Society
• /
• 2004.10b
• /
• pp.270-273
• /
• 2004

The initial thermal analysis needs to be fast and efficient to reduce the feedback time for the optimal electronic equipment designing. In this study, a thermal model is developed by using power consumption measurement values of each functional breadboard, that is, semi-empirical power dissipation method. In modeling heat dissipated EEE parts, power dissipation is imposed evenly on the EEE part footprint area which is projected to the printed circuit board, and is called surface heat model. The application of these methods is performed in the development of a command and telemetry unit (CTU) for a geostationary satellite. Finally, the thermal cycling test is performed to verify the applied thermal analysis methods.

• Proceedings of the IEEK Conference
• /
• 2000.07a
• /
• pp.351-354
• /
• 2000

In the past, we proposed an IDDQ testable design method for static CMOS PLA circuits. All bridging faults can be detected in NOR planes of our testable designed PLA circuits by IDDQ testing with 4 kinds of test input vectors which are independent of the logical functions to be realized. However, the testable designed PLA circuits consume large power in the normal operation. In this paper, a new IDDQ testable design method is proposed and evaluated by some experiments. The experimental results show that the PLA circuit designed with our method can work with low power consumption than the previous one.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2009.10a
• /
• pp.677-680
• /
• 2009

DC influence between pixel electrode and alignment layer (AL) in in-plane switching mode LCD was analyzed through DC equivalence-circuit equation induction, DC charge-discharge simulation, luminance and residual-DC measurement systems using test patterned (TP) cell. DC discharging rate (DDR) of single layer electrode was faster than that of double layer electrode and DDR of low resistance AL was faster than that of high resistance AL. DC discharging characteristics had a close relation to layer number and resistance between two electrodes.

• Journal of the Korea Society for Simulation
• /
• v.11 no.2
• /
• pp.17-29
• /
• 2002

There is an increasing interest in high-performance A/D(Analog-to-Digital) converters for use in integrated analog and digital mixed processing systems. Pipeline A/D converter architectures coupled with BiCMOS process technology have the potential for realizing monolithic high-speed and high-accuracy A/D converters. In this paper, the design of 12bit pipeline BiCMOS A/D converter presented. A BiCMOS operational amplifier and comparator suitable for use in the pipeline A/D converter. Test/simulation results of the circuit blocks and the converter system are presented. The main features is low distortion track-and-hold with 0-300MHz input bandwidth, and a proprietary 12bit multi-stage quantizer. Measured value is DNL=${\pm}$0.30LSB, INL=${\pm}$0.52LSB, SNR=66dBFS and SFDR=74dBc at Fin=24.5MHz. Also Fabricated on 0.8um BiCMOS process.

• Journal of the Semiconductor & Display Technology
• /
• v.14 no.4
• /
• pp.67-71
• /
• 2015

Product of technology developed in this study is an external interface for controlling the equipment of pendant key remote control system circuit board, and it is used in the electronic component test equipment system. Main control system module is in the role as a device for controlling the various control devices that make up the integrated system for microscopic examination at the request of the host computer engineers to control the inspection equipment. The pentane-key interface module to its role as a device for controlling the various control devices that make up the integrated system for microscopic examination at the request of the host computer for the engineer to control the inspection equipment. Development of the control system can be expected in the configuration of a system for efficient and accurate inspection of high-precision parts.

• Progress in Superconductivity and Cryogenics
• /
• v.7 no.3
• /
• pp.17-20
• /
• 2005

AC loss of a high $T_c$ superconducting conductor has a strong influence on the economic viability of a superconducting fault current limiter, which offers an attractive means to limit short circuit current in the power systems. Therefore, several samples of the fault current limiting coils have been fabricated and the effect of conductor's arrangement and current direction on AC loss characteristics investigated experimentally The test result shows that the AC losses measured in the fault current limiting coils depend significantly on the conductor's arrangement. Futhermore, they are also considerably influenced by the conductor's current direction. The AC loss measured in the face-to-face arrangement is smallest among the fault current limiting coil samples.