Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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IDDQ Testable Design of Static CMOS PLAs with tow rower Consumption

  • Hoshika, Hiroshi (Department of Electrical and Electronic Engineering, Faculty of Engineering, The Univ. of Tokushima) ;
  • Hashizume, Masaki (Department of Electrical and Electronic Engineering, Faculty of Engineering, The Univ. of Tokushima) ;
  • Yotsuyanagi, Hiroyuki (Department of Electrical and Electronic Engineering, Faculty of Engineering, The Univ. of Tokushima) ;
  • Tamesada, Takeomi (Department of Electrical and Electronic Engineering, Faculty of Engineering, The Univ. of Tokushima)
  • Published : 2000.07.01
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Abstract

In the past, we proposed an IDDQ testable design method for static CMOS PLA circuits. All bridging faults can be detected in NOR planes of our testable designed PLA circuits by IDDQ testing with 4 kinds of test input vectors which are independent of the logical functions to be realized. However, the testable designed PLA circuits consume large power in the normal operation. In this paper, a new IDDQ testable design method is proposed and evaluated by some experiments. The experimental results show that the PLA circuit designed with our method can work with low power consumption than the previous one.

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