• Journal of the Korean Institute of Gas
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• v.14 no.3
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• pp.14-20
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• 2010

This paper was studied on the explosion hazard by spark discharge of the lithium-ion battery. The experimental samples were chosen lithium-ion battery(general, notebook) which were used for source of portable equipment. The IEC(International Electrotechnical Commission) type spark ignition test apparatus and experimental gases such as methane, propane, ethylene or hydrogen were used for explosiveness test. It was confirmed through the experiment that the explosion hazard by spark discharge. Also, it was used thermal imager for confirm that spontaneous ignition possibility by short-circuit. As the result, this paper verified that lithium-ion battery should be used and designed by special attention safety in the hazardous zone which is existed explosiveness gas.

• Transactions of the Korean Society of Automotive Engineers
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• v.21 no.6
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• pp.147-154
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• 2013

This study reports on the development and investigation of a BMS module using a new algorithm on the driving performance and battery life of electric vehicles. Here, the initial SOC was calculated using an open circuit voltage (OCV) method and a current integral method was later applied to the BMS module. We verified the performance of the BMS module by comparing both the results of the in-vehicle test and the BMS simulator test. Our verification test showed good agreement between the results of experiments and simulation with a small error of ${\pm}0.8%$. Here, we confirmed that the present, newly-developed BMS module not only can predict the battery life but can also monitor SOC, pack voltage, and current temperature.

• Nuclear Engineering and Technology
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• v.53 no.10
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• pp.3335-3343
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• 2021

The impact of gamma radiation on a commercial off the shelf microcontroller board has been investigated. Three different tests have been performed to ascertain the radiation tolerance of the device from a nuclear decommissioning deployment perspective. The first test analyses the effect of radiation on the output voltage of the on-board voltage regulator during irradiation. The second test evaluated the effect of gamma radiation on the voltage characteristics of analogue and digital inputs and outputs. The final test analyses the functionality of the microcontroller when using an external, shielded voltage regulator instead of the on-board voltage regulator. The results suggest that a series of latch-ups occurs in the microcontroller during irradiation, causing increased current drain which can damage the voltage regulator if it does not have short-circuit protection. The analogue to digital conversion functionality appears to be more sensitive to gamma radiation than digital and analogue output functionality. Using an external, shielded voltage regulator can prove beneficial when used for certain applications. The collected data suggests that detaching the voltage regulator can extend the lifespan of the platform up to approximately 350 Gy.

• Journal of the Korea Computer Industry Society
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• v.10 no.4
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• pp.143-150
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• 2009

Remote control service, monitoring, gear service of information electronic appliance, various services of security service and so on of Home network that is by link of Ubiquitous environment are offered. These services need verification process through priority test to use and are changed. If test using actuality information electronic device for test, much expenses and time may be invested. Home network test bed offers softness of research using control model and simulator, in this paper, Wish to design and embody home network test bed to do environment construction of home network and test of application service. Because use istent power line just as it is without necessity to establish circuit in addition by solution of home network testbed, expense costs to be less and establishment used easy PLC. Also, propriated Wireless sensor network that use Zigbee by solution of home network testbed. Appliance check and monitor square do by Home Auto that know embodied, and embodied by Home Gateway that interlink terminals of Home Auto and out of.

• The Transactions of the Korea Information Processing Society
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• v.3 no.3
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• pp.572-580
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• 1996

This paper describes a test generation method for sequential circuits which improves the application limits of the IPMT method by applying the partial scan design to the IPMT method. To solve the problem that the IPMT method requires enormous computation time in image computation, and generates test patterns after the partialscan design is introduced to reduce test complexity. Scan flip-flops are selected for the partial scan design according to the node size of the state functions of a sequential circuit in their binary decision diagram representations. Experimental results on ISCAS'95 benchmark circuits show that a test generator based on our method has achieved 100% fault coverage by use of either 20% scan FFs for s344, s349, and s420 or 80% scan FFs for sl423. However, test gener-ators based on the previous IPM method have not achieved 100% fault coverage for those circuits.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.31 no.1C
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• pp.29-38
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• 2011

The smaller diameter cone penetrometer has been widely used to estimate the characteristics of local area due to high vertical resolution. The half-bridge cirucits have been adopted to measure the mechnical strength of soil through the smaller diameter cone penetrometer due to the limitation of the areas for configuring the full-bridge circuit. The half-bridge circuit, however, is known as being easily affected to the temperature variation. The objective of this study suggests the temperature-compensated method in mini-cones. The diameter and length of the mini-cone is designed to 15mm and 56mm. The load cell of the mini-cone is extended about 54mm on the behind of the mini-cone to reflect the only temperature variation. The full-bridge circuit is installed to measure the temperature-compensated values in the mini-cone and the half-bridge circuit is also organized to compare the temperature compensated values with uncompensated values. The seasonal variation tests are performed to define the effect of temperature variation under summer and winter temperature condition. The densification tests are also carried out to investigate temperature effects during penetration. The measured mechanical resistances with temperature-compensated method show more reliable and reasonable values than those measured by thermal uncompensated system. This study suggests that the temperature-compensated method of the mini-cone may be a useful technique to obtain the more reliable resistances with minimizing the temperature effect.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1868-1876
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• 2010

In this paper, we design a 256-bit EEPROM IP using only logic process-based devices. We propose EEPROM core circuits, a control gate (CG) and a tunnel gate (TG) driving circuit, to limit the voltages between the devices within 5.5V; and we propose DC-DC converters : VPP (=+4.75V), VNN (-4.75V), and VNNL (=VNN/3) generation circuit. In addition, we propose switching powers, CG_HV, CG_LV, TG_HV, TG_LV, VNNL_CG, VNNL_TG switching circuit, to be supplied for the CG and TG driving circuit. Simulation results under the typical simulation condition show that the power consumptions in the read, erase, and program mode are $12.86{\mu}W$, $22.52{\mu}W$, and $22.58{\mu}W$ respectively. Furthermore, the manufactured test chip operated normally and generated its target voltages of VPP, VNN, and VNNL as 4.69V, -4.74V, and -1.89V.

• Proceedings of the KIEE Conference
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• 2006.07a
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• pp.486-487
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• 2006

The authors have studied on the application of IEC 60364-4-44 to Korean electrical installations of buildings from 2004 sponsored by Korean ministry of commerce, industry and energy and the test field is established in K.E.R.I. (Korea Electrotechnology Research Institute). This paper presents the summary results of establishment of test field and analysis for the application of IEC 60364 in Korea. IEC 60364-4-44 provides rules for the protection against the effects of conducted and radiated disturbances on electrical installations. Especially this standard deals with the protection of low voltage facility against the ground fault in the high voltage side of power distribution system. Many countries define the regulations on the use and production of electrical facilities based on their own power system and technical references which are considered to be suitable for them. The background of circuit of IEC 60364-4-44 is based on the ungrounded system as most of European countries. However, since Korean electric power distribution system is based on multi-grounding system different from European system, it is necessary to evaluate or prove the effect of the IEC 60364-4-44 for introducing and applying it to the domestic grounding system as a Korean standard. This paper presents the establishment of test field to get background data to introduce the IEC 60364-4-44 and to evaluate the standard is applicable to domestic rule for the protection against ground fault through the related test

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.37-44
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• 2006

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller is simple in terms of test procedure and is small in terms of area overhead.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.292-301
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• 2001

IDDQ Testing is a very effective testing method to detect many kinds of physical defects occurred in CMOS VLSI circuits. In this paper, we consider the most commonly occurring bridging faults in current CMOS technologies and develop pattern generator for IDDQ testing using efficient IDDQ test algorithms. The complete set of bridging faults between every pair of all nodes(internal and external nodes) within circuit under test is assumed as target fault model. The merit of considering the complete bridging fault set is that layout information is not necessary. Implemented test pattern generator uses a new neighbor searching algorithm and fault collapsing schemes to achieve fast run time, high fault coverage, and compact test sets. Experimental results for ISCAS benchmark circuits demonstrate higher efficiency than those of previous methods.