• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.1643-1645
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• 2005

A newly-built inverter has to undergo a series of stress tests in the final stage of production line. This can be achieved by connecting it to a dynamometer consisting of a three-phase machine joined by a rigid shaft to a DC load machine. The latter is controlled to create some specific load characteristic needed for the test. In this paper a test method is proposed, in which no mechanical equipment is needed. The suggested test stand consists only of a inverter to be tested and a simulator converter. Both devices are connected back- to-back on the AC-side via smoothing reactors. The simulator operates in real-time as an equivalent load circuit, so that the device under test will only notice the behaviour of a three-phase machine under consideration of the load. In odor to wove rightness of the suggested test method, the simulation and actural experiment rallied out emulation for a 2.2kW induction motor.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.120-123
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• 2000

In this paper, A target architecture and interface synthesizer are proposed for processor-embedded codesign. The target architecture has the form of ARM processor based on AMBA. The interface synthesizer automatically generates an interface circuit for the communication between HW and SW. A memory map is used as the communication channel and an interrupt-based interface is applied for synchronized communication between HW and SW modules. In order to verify the function and performance of proposed target architecture and the interface synthesizer, practical test example is applied. Experimental results show the proposed interface synthesizer functioned correctly in the HW/SW codesign environment.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.52 no.3
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• pp.101-106
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• 2003

The high temperature superconductor transformers gain interests from the industries. This paper described construction and test results of 10㎸A HTS transformer Three phase transformer with double pancake windings were constructed. To reduce the leakage magnetic field, secondary coil were placed between the two primary coils. BSCCO-2223 wire. silicon sheet steel core and FRP cryostats were used to construct the transformer. Three coils were stacked in one cryostat. Two double pancake coils were connected in series for the primary coil and one double pancake coil was used for the secondary coil. Total number of turns of the primary winding and the secondary winding were 112turns and 98urns, respectively, The rated voltages of each winding were 440/220V. The rated currents of each winding were 13.1/26.2A. After the tests of basic properties of the three phase HTS transformer using no-load test, short-circuit test and full-load test, continuous operation of 100 hours with pure resistive load has been carried out. Test results proved over-load capability and reliability of the HTS transformer.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.8
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• pp.9-17
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• 2020

Recently, RES (renewable energy source) projects have been spreading all over the world as an alternative to solve the shortage of energy and environmental problems caused by fossil fuel consumption. The Korean government also supported the policy and demonstration project to increase the proportion of renewable energy to 63.8[GW] until 2030, which is 20[%] of the total power generation. On the other hand, output loss of a PV array can occur when the surrounding high-rise buildings and trees shade a PV array. Therefore, this paper proposes an algorithm to improve the output loss of a PV array, which electrically changes a circuit configuration of PV modules by wiring and switching devices. Furthermore, this study modeled a PV system based on PSIM S/W, which was composed of a PV array, a circuit configuration device, and a grid-connected inverter. From the simulations results with the modeling and test device, the existing method showed no output when 50% of the shade occurs in PV modules. In contrast, the proposed method could produce the output because the voltage in the PV module could be restored to 246[V], and the operation efficiency of the PV system could be improved by the operation algorithm of the circuit configuration device.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.2
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• pp.128-137
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• 1999

Recently the pelionnance of CO2 arc welding machine has been advanced significantly through the adoption of i invelter circuit topology. which made it possible to improve welding perfonnances such as spatter generation and bead s state. But the conventional inverter arc welding machine generates constant output voltage which cause much spatter g generation dUling short-circuit and arc start time because it is unable to control output current instantaneously. So this p paper representes wavefCnm controlled inverter arc welding machine which control the wavefonn of welding current and t thus to suppress the spatter generation. And the system designed in this paper is the digital controller using single chip m microprocessor of 80C196KC. As a result of perfonnance test for this system, the spatter generation is reduced and s shOlt-circuit time period is stabilized compared to conventional one. And more by using switched mode rectifier for A AC/DC power convelter. unity power factor is maintained and low order halmonic spectrum is supressed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.34-43
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• 2008

An OpenLDI receiver circuit for flat-panel display systems was designed and fabricated using $1.8-{\mu}m$ high-voltage CMOS technology. Designed circuit roughly consists of DLL circuit and parallelizers, which recovers clock and parallelize data bits, respectably. It has one clock input and four data inputs. Measurement results showed that it successfully recovers clock signal from input whose frequency is $10Mhz{\sim}65Mhz$, which corresponds data rate of $70Mbps{\sim}455Mbps$ per channel, or $280Mbps{\sim}1.82Gbps$ when all of the four data channels were utilized. A commercial LCD monitor was modified into a test-bench and used for video data transmission at clock frequency of 49Mhz. In the experiment, power consumption was 19mW for core block and 82.5mW for output buffer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.1254-1257
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• 2004

This paper presents a built-in current sensor(BICS) that can detect defects in CMOS integrated circuits through current testing technique - Iddq test. Current test has recently been known to a complementary testing method because traditional voltage test cannot cover all kinds of bridging defects. So BICS is widely used for current testing. but there are some critical issues - a performance degradation, low speed test, area overhead, etc. The proposed BICS has a two operating mode- normal mode and test mode. Those methods minimize the performance degradation in normal mode. We also used a current-mode differential amplifier that has a input as a current, so we can realize higher speed current testing. Furthermore, only using 10 MOSFETS and 3 inverters, area overhead can be reduced by 6.9%. The circuit is verified by HSPICE simulation with 0.25 urn CMOS process parameter.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2004.10a
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• pp.263-268
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• 2004

In the present study, a Nd;YAG Laser (pulse type) was used to emit ultrasonic signals to a test material. In addition, a total ultrasonic investigation system was designed by adopting a Fabry-Perot interferometer, which receives ultrasonic signals without any contact. For non-destructive test SM45C, which contains some flaws was used as a test material. Because it is easy to align light beam in receiver, and the length of the light beam does not change much even if convex mirror leans towards one side, confocal Fabry-Perot interferometer, which has stable frequency, and PI control are used to correct interfered and unstable signals from temperature, fluctuation and time shift of laser frequency. Stable signals are always obtained by the feedback of PI circuit signals in the confocal Fabry-Perot interferometer. The type, size and position of flaws inside the test material were examined by achieving the stabilization of an interferometer. This study presented a useful method, which could quantitatively investigate the fault of objects by using a Fabry-Perot interferometer.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1674-1676
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• 2002

In this paper, High Frequency PD measuring system using directional coupler sensors(DCS) is introduced. Especially the principles of the DCS and characteristics of the system are introduced. Evaluation of this system was carried by an adoption to the test circuit of 345kV XLPE $2000mm^2$ cable and EB-A, EB-G, PIJ, PNJ. In the test a PD measurement was carried out without shieldroom and under the on-line state and in the high frequency range at the remote site from the test object. The test result was satisfactory and this is due to the use of DCS and using a high frequency range and specific filter for radio and TV signal and low pass. This system can be used to the test of a new construction of cable and accessories and measuring of long-term deterioration of cable and accessories. And this will bring us the reliability of a power transmission.

• Progress in Superconductivity
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• v.4 no.1
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• pp.74-79
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• 2002

High-speed probe made to test single flux quantum(SFQ) circuits was comprised of semi-rigid coaxial cables and microstrip lines. The impedance was set at 50 $\Omega$to carry high-speed signals without much loss. To do performance test of high-speed probe, we have attempted to fabricate a test chip which has a coplanar waveguide(CPW) structure. Electromagnetic simulation was done to optimize the dimension of CPW so that the CPW structure has an impedance of 50$\Omega$, matching in impedance with the probe. We also used the simulation to investigate the effect of the width of signal line and the gap between signal line and ground plane to the characteristics of CPW structure. We fabricated the CPW structure with a gold film deposited on Si wafer whose resistivity was above $1.5\times$10$_4$$\Omega$.cm. The magnitudes of S／sub 21／ of CPW at 6 ㎓ in simulations and in the actual measurements done with a network analyzer were: -0.1 ㏈ and -0.33 ㏈ (type A),-0.2 ㏈ and -0.48 ㏈ (type B), respectively. Using the test chip, we have successfully tested the performance of high-speed probe made for SFQ circuits. The probe showed the good performance overthe bandwidth of 10 ㎓.