• ETRI Journal
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• v.26 no.6
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• pp.520-534
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• 2004

As the density of memories increases, unwanted interference between cells and the coupling noise between bit-lines become significant, requiring parallel testing. Testing high-density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built-in self-test (BIST) algorithm for neighborhood pattern-sensitive faults (NPSFs) and new neighborhood bit-line sensitive faults (NBLSFs). Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a four-cell layout is utilized. This four-cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck-at faults, transition faults, conventional pattern-sensitive faults, and neighborhood bit-line sensitive faults.

• Progress in Superconductivity and Cryogenics
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• v.11 no.2
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• pp.33-36
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• 2009

A 1 MW class HTS (High-Temperature Superconducting) synchronous motor has been developed. This motor is aimed to be utilized for industrial application such as large motors operating in large plants. The HTS field coil of the developed motor is cooled by way of neon thermo siphonmechanism and the stator (armature) coil is cooled by water through hollow copper conductor. This paper also describes evaluation of some electrical parameters from performance test results of our motor, which was conducted at steady state in generator mode and motor mode. Open and short circuit tests were conducted in generator mode while a 1.1 MW rated induction machine was rotating the HTS machine. Electrical parameters such as mutual inductance and synchronous inductance are deduced from these tests. Load test was done upto rating torque during motor mode and efficiency was measured at each load torque.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.10
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• pp.1875-1880
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• 2011

This paper proposes a battery model applicable to Autonomie environment. Also, a various of experiment is implemented for validation. The proposed battery model modifies Randles equivalent circuit and battery parameters are extracted from pulsed current tests. The parameters are two-dimensional function of current and SOC(State of Charge). The battery model is developed in the Matlab/Simulink and is implemented for NiMH Panasonic HHR650D and compared with pulsed current discharge curves. The simulation results validate the accuracy of the proposed model and the model is also tested by adding it on Autonomie for HEV application. Constant current charge/discharge, pulsed current test that can be used to extract battery parameter are performed and test results are used to build up the proposed battery model for Autonomie.

• Proceedings of the KSR Conference
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• 2005.05a
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• pp.291-298
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• 2005

This paper describes the characteristic feather of propulsion system adopting mass production. The train formation is composed of 4 cars by 2 Motor cars and 2 Train cars. Acceleration rate must be 3.0 km/h/s or more when the car starts up to 35km/h by 16ton of passenger load. The system information supervision is easy because the system is controlled to perfect digital circuits, all information of an action is stored in a memory and is managed. The control system is composed of a fully digital circuit and a high level software such as C language. The DSP TMS320C31 is used for main processor and has the capability of 50MHz, 32bit floating point operation and has a C compiler. Therefore, the implementation of control algorithm and the change of function are easy. VVVF inverter using IGBT conducted variable combined test, environment test using chamber, interface test and field test etc.

• Journal of Mechanical Science and Technology
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• v.18 no.5
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• pp.798-807
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• 2004

A testing system was developed to improve the reliability of printhead and several printheads were tested. We developed a thermally driven monolithic inkjet printhead comprising dome-shaped ink chambers, thin film nozzle guides, and omega-shaped heaters integrated on the top surface of each chamber. To perform a fatigue test of an inkjet printhead, the testing system automatically detects a heating failure using a Wheatstone bridge circuit. Various models were designed and tested to develop a more reliable printhead. Two design parameters of the width of reinforcing layer and heater were investigated in the test. Specially., the reinforcing layer was introduced to improve the fatigue life of printhead. The life-span of heater with a reinforcing layer was longer than that without a reinforcing layer. The wider the heater was, the longer the life of printhead was.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.35 no.9
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• pp.1137-1143
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• 2011

The IHX (intermediate heat exchanger) of a VHTR (very high-temperature reactor) is a core component that transfers the high heat generated by the VHTR at $950^{\circ}C$ to a hydrogen production plant. Korea Atomic Energy Research Institute manufactured a small-scale prototype of a PCHE (printed circuit heat exchanger) that was being considered as a candidate for the IHX. In this study, as a part of high-temperature structural integrity evaluation of the small-scale PCHE prototype, we carried out high-temperature structural analysis modeling and macroscopic thermal and elastic structural analysis for the small-scale PCHE prototype under small-scale gas-loop test conditions. The modeling and analysis were performed as a precedent study prior to the performance test in the small-scale gas loop. The results obtained in this study will be compared with the test results for the small-scale PCHE. Moreover, these results will be used in the design of a medium-scale PCHE prototype.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.54-60
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• 2007

This paper proposes a built-in-self-repair (BISR) structure using 2-dimensional spare memory to effectively self-repair faults of an embedded memory. In case of multiple faults in the same row (column) of an embedded memory, the previous method using 1-D spare column (row) memory needs the same number of spare memory columns (rows) as the number of faults to self-repair them. while the new method using 2-D spare memory needs only one spare row (column) to self-repair them. Also, the virtual divided memory is adopted to be able to self-repair using not a full spare column memory but the only partial spare column memory corresponding to the faults. A self-repair circuit with $64\times1-bit$ core memory and $2\times8$ 2-D spare memory is designed. And the circuit includes a built-in-self-test block using the 13N March algorithm. The circuit has been implemented using the $0.25{\mu}m$ MagnaChip CMOS process and has $1.1\times0.7mm^2$ chip area with 10,658 transistors.

• ETRI Journal
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• v.32 no.6
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• pp.969-971
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• 2010

Based on a de-embedding technique, a new method is proposed which is capable of evaluating chip impedance behavior over absorbed power in flip-chip bonded UHF radio frequency identification transponder ICs. For the de-embedding, four compact co-planar test fixtures, an equivalent circuit for the fixtures, and a parameter extraction procedure for the circuit are developed. The fixtures are designed such that the chip can absorb as much power as possible from a power source without radiating appreciable power. Experimental results show that the proposed modeling method is accurate and produces reliable chip impedance values related with absorbed power.

• ETRI Journal
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• v.35 no.1
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• pp.150-153
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• 2013

In this letter, a compact and fully printed composite right- and left-handed (CRLH) dual-band power divider is proposed. The branches of the conventional Wilkinson power divider are replaced by subwavelength CRLH phase-shift lines having $+90^{\circ}$ for one frequency and $-90^{\circ}$ for another frequency for dual-band and miniaturization performance. Equations are derived for the even- and odd-mode analysis combined with the dual-band CRLH circuit. A PCS and a WLAN band are chosen as the test case and the circuit approach agrees with the CAD simulation and the measurement. Additionally, the CRLH property is shown with the dispersion diagram and the eightfold size reduction is noted.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.11-20
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• 1998

Fault simulatior has been used to compute exact fault coverages of test vectors for digial circuits. But it is time consuming because execution time is proportional to square of circuit size. Recently, several algorithms for testability analysis have been published to cope with these problems. COP is very fast and accurate but cannot be used for sequential circuits, while STAFAN can be used for sequential circuits but needs vast amount of execution time due to good circuit simulation. We proposed EXTASEC which gave fast and accurate fault coverage. But it shows noticeable errors for a few sequential circuits. In this paper, it is shown that the inaccuracy is due to uninitializble flipflops, and we propose ITEM to improve the EXTASEC algorithm. ITEM is an improved evaluation method of fault coverage by analysis of backward lines and uninitializable flipflops. It is expected to perform efficiently for very large circuits where execution time is critical.