• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.271-274
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• 2003

This paper presents a Built-in Current Sensor that detect defects in CMOS integrated circuits using the current testing technique. This scheme employs a cross-coupled connected PMOS transistors, it is used as a current comparator. Our proposed scheme is a negligible impart on the performance of the circuit undo. test (CUT). In addition, in the normal mode of the CUT not dissipation extra power, high speed detection time and applicable deep submicron process. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects. The entire area of the test chip is $116{\times}65{\mu}m^2$. The BICS occupies only $41{\times}17{\mu}m^2$ of area in the test chip. The area overhead of a BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix $0.35{\mu}m$ 2-poly 4-metal N-well CMOS technology.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.5
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• pp.283-288
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• 2000

In this work, small-size, high-performance simple solenoid-type RF chip inductors utilizing an Al2O3 core material were investigated. Copper (Cu) wire with $40\mum$ diameter was used as the coils and the size of the chip inductor fabricated in this work was $2.1mm\times1.5mm\times1.0mm$. The external current source was applied after bonding Cu coil leads to gold pads electro-plated on each end of backsides of a core material. High frequency characteristics of the inductance (L), quality factor (Q), and impedance (Z) of developed inductors were measured using an RF Impedance/Material Analyzer (HP4291B with HP16193A test fixture). This HP4291B was also used to obtain the equivalent circuit and its circuit parameters of the chip inductors. This HP4291B was also used to obtain the equivalent circuit and its circuit parameters of the chip inductors. The developed inductors have the self-resonant frequency (SRF) of 1.1 to 3.1 GHz and exhibit L of 22 to 150 nH. The L of the inductors decreases with increasing the SRF. The Z of the inductors has the maximum value at the SRF and the inductors have the quality factor of 70 to 97 in the frequency range of 500 MHz to 1.5 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.7
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• pp.493-502
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• 2001

This paper propose a new built-in current sensor(BICS) for current testing that has some advantages compared with conventional logic testing. The designed BICS detects the fault in circuit under test (CUT) and makes a Pass/Fail signal by comparison between CUT current and duplicated inverter current. The proposed circuit consists of a differential amplifier, a comparator and a inverter. It requires 10 MOSFETs and 3 inverters. Since the designed BICS do not require the extra clock, the added extra pin is only one output pin. The mode selection is not used in this circuit. Therefore we can apply the circuit to on-line testing. The validity and effectiveness are verified through the HSPICE simulation of circuits with defects. When CUT is a 8$\times$8 parallel multiplier, area overhead of the BICS is about 4.34%.

• Progress in Superconductivity and Cryogenics
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• v.21 no.1
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• pp.31-35
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• 2019

The lumped-parameter circuit model for a no- insulation (NI) high temperature superconductor (HTS) magnet has been well understood after many experimental and analytic studies over a decade. It successfully explains the non-linear charging behaviors of NI magnets. Yet, recently, multiple groups reported that the post-quench electromechanical behaviors of an NI HTS magnet may not be well explained by the lumped circuit model. The characteristic resistance of an NI magnet is one of the key parameters to characterize the so-called "NI behaviors" of an NI magnet and recently a few groups reported a potential that the characteristic resistance of an NI magnet may substantially vary during a quench. This paper deals with this issue, the increment of contact resistance of the no-insulation (NI) REBCO magnet during a quench and its impact on the post-quench behaviors. A 7 T 78 mm NI REBCO magnet that was previously built by the MIT Francis Bitter Magnet Laboratory was chosen for our simulation to investigate the increment of contact resistance to better duplicate the post-quench coil voltages in the simulation. The simulation results showed that using the contact resistance value measured in the liquid nitrogen test, the magnitude of the current through the coil must be much greater than the critical current. This indicates that the value of the contact resistance should increase sharply after the quench occurs, depending on the lumped circuit model.

• The Transactions of the Korea Information Processing Society
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• v.5 no.9
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• pp.2378-2387
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• 1998

This thesis proposes a design algorithm of an efficient space response compactor for Built-In Self-Testing of VLSI circuits. The proposed design algorithm of space compactors can be applied independently from the structure of Circuit Cnder Test. There are high hardware overhead cost in conventional space response compactors and the fault coverage is reduced by aliasing which maps faulty circuit's response to fault-free one. However, the proposed method designs space response compactors with reduced hardware overheads and does not reduce the fault coverage comparing to conventional method. Also, the proposed method can be extended to general N -input logic gate and design the most efficient space response L'Ompactors according to the characteristies of output sequence from CUT. The prolxlsed design algorithm is implemented by C language on a SUN SPARC Workstation, and some experiment results of the simulation applied to ISCAS'85 benchmark circuits with pseudo random patterns generated bv LFSR( Linear Feedback Shift Register) show the efficiency and validity of the proposed design algorithm.

• Fire Science and Engineering
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• v.18 no.1
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• pp.18-23
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• 2004

This paper describes the minimum ignition limits for propane-air 5.25 Vol.% mixture gases in low voltage inductive circiuts. The improved effects on the ignition limit are studied by parallel safety components(resistors) for propane-air 5.25 Vol.% mixture gas in low voltage inductive circuits. The experimental devices used in this test are the IEC type spark ignition test apparatus. The minimum ignition limits are controlled by the values of current in inductive circuit. Energy supplied from electric source is first accumulated at the inductance, it's extra energy is working as ignition source of the explosive gas. The improved effects on the ignition limit are respectively obtained as the maximum rising rate of 330% by composing parallel circuits between inductance and resistor as compared with disconnecting inductance with the safety components. The more values of inductance increase the higher improved effects of ignition limit rise. The less values of resistor the higher improved effects of ignition limit rise. It is considered that the result can be used for not only data for researches and development of intrinsically safe explosion-proof machines which are applied equipment and detectors used in dangerous areas but also for datum for its equipment tests.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1811-1813
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• 2001

In order to obtain the useful data for quality control of the pole transformer and supply the stable electric power in distribution line, The evaluation of performance for low-loss pole transformer had been performed for new products and ones under operation for several years in distribution line. As the results, we found that the rate of fail were very high in gaskette, short-circuit strength and temperature-rise test, especially 48 percent in gaskette test.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.1
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• pp.199-202
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• 2009

Scan design is currently the most widely used structured Design For Testability approach. In scan design, all storage elements are replaced with scan cells, which are then configured as one or more shift registers(also called scan chains) during the shift operation. As a result, all inputs to the combinational logic, including those driven by scan cells, can be controlled and all outputs from the combinational logic, including those driving scan cells, can be observed. The scan inserted design, called scan design, is operated in three modes: normal mode, shift mode, and capture mode. Circuit operations with associated clock cycles conducted in these three modes are referred to as normal operation, shift operation, and capture operation, respectively. In spite of these, scan design methodology has defects. They are power dissipation problem and test time during test application. We propose a new methodology about scan shift clock operation and present low power scan design and short test time.

• Journal of the Korea Knowledge Information Technology Society
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• v.12 no.4
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• pp.539-550
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• 2017

In this paper, we designed, fabricated and tested an UHF band cylindrical dipole array antenna. In the proposed antenna, cylindrical dipoles were vertically arranged in four stages. A parallel structure feeding circuit was installed inside the cylindrical dipole and mounted so as to be broadband matching. The feeding circuit was installed at the center of the cylindrical dipole to optimize the gain flatness characteristic of the azimuth direction omnidirectional radiation pattern. Minimizing the difference between the signals branched from the feeding circuit and realizing the symmetry of the radiation pattern. The required specifications are more than 11.2% bandwidth in UHF band, above 6dBi antenna gain, standing wave ratio of 2:1 or less, less than ${\pm}1dB$ gain flatness in azimuth radiation pattern, more than 13 degrees in elevation radiation pattern of 3dB beamwidth. We confirmed the possibility of implementation through M&S and verified the result of M&S through production and testing. The test results are 11.2% bandwidth in the UHF band, 6.30 to 8.31 dBi gain, 1.53:1 standing wave ratio or less, within ${\pm}0.2dB$ gain flatness in the azimuth radiation pattern, elevation radiation pattern of 3dB beam width was 15.62 to 15.84 degrees. The test result meets all requirements specifications.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.3_4
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• pp.186-193
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• 2003

In recent years the complexity of digital systems has increased dramatically. Although semiconductor manufacturers try to ensure that their products are reliable, it is almost impossible not to have faults somewhere in a system at any given time. As complexity of circuits increases, the necessity of more efficient organized and automated methods for test generation is growing. But, up to now, most of popular and extensive methods for test generation nay be those which sequentially produce an output for an input pattern. They inevitably require a lot of time to search each fault in a system. In this paper, corresponding test patterns are generated through the partitioning method among those based on the exhaustive method. In addition, the method, which can discovers faults faster than other ones that have been proposed ever by inserting a pattern in parallel, is designed and implemented.