• 한국신재생에너지학회:학술대회논문집
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• 2009.11a
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• pp.431-434
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• 2009

Conceptual study of an open-circuit type low-speed wind tunnel for test of wind turbine blade is conducted. The tunnel is constituted of a settling chamber, a contraction, closed and open test sections, a diffuser, two corners, a cross leg and a fan and motor. For the performance test, the closed test section width of 1.8 m, height of 1.8 m and length of 5.25 m is selected. The open test section with dimension width of 1.8 m, height of 1.8 m and length of 4.14 m is adopted for aeroacoustic test. The contraction ratio is 9 to 1 and maximum speed in the closed test section is 67 m/sec. Input power in the tunnel is about 238 kW and its energy ratio is 3.6. The wind tunnel designed in present study will be an effective tool in research and development of wind turbine.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.7
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• pp.597-605
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• 2015

Negative impedance converter(NIC)-based non-Foster impedance matching is proposed for an electrically small antenna. The antenna considered in this work is a resistively loaded vee dipole(RVD) antenna, which has considerable reflection at the feed point because of its large negative input reactance. The non-Foster matching circuit built near the feed point consists of two-stage NIC circuit and a capacitor connected between the stages. The NIC is realized by using operational amplifiers(op-amps) and resistors. The circuit is designed by considering of the input impedance according to the finite open-loop gain of the practical NICs. The stability test of the impedance-matched RVD antenna is performed. The non- Foster matching circuit is implemented with the RVD antenna. The measured impedance demonstrates that the proposed non-Foster matching circuit effectively reduces the input reactance of the RVD antenna.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.251-265
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• 2001

As the device scaling proceeds, the operating voltage(VDD) of giga-bit DRAMs is expected to be reduced to 1.5V or down, fir improving the device reliability and reducing the power dissipation. Therefore the low-voltage circuit design techniques are required to implement giga-bit DRAMs. In this work, state-of-art low-voltage DRAM circuit techniques are reviewed, and four kinds of low-voltage circuit design techniques are newly proposed for giga-bit DRAMs. Measurement results of test chips and SPICE simulation results are presented for the newly proposed circuit design techniques, which include a hierarchical negative-voltage word-line driver with reduced subthreshold leakage current, a two-phase VBB(Back-Bias Voltage) generator, a two-phase VPP(Boosted Voltage) generator and a bandgap reference voltage generator.

• Proceedings of the KWS Conference
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• 2006.10a
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• pp.136-138
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• 2006

Recently a lots of problems have observed in high densified and high integrated electronic components. One of them is ion migration phenomena, which induce the electrical short of electrical circuit. Ion migration phenomena has been observed in the field of exposing the specific environment and using for a long time. Also as the RoHS restriction was started in July 1st, 2006, Pb-free solder was utilized in electronics assemblies. In this case, it is very important to compatible between components and printed circuit board(PCB), thus surface treatment materials of PCB was changed to Sn, Sn-3.0Ag-0.5Cu, Cu. Therefore these new application become to need to reevaluate the sensitivity about electrochemical ion migration. This study was evaluated the occurrence time of electrochemical ion migration using by water drop test. We utilized PCB(printed circuit board) having a comb pattern as follows 0.1, 0.318, 0.5, 1.0 mm pattern distance. Sn-3.0Ag-0.5Cu and Sn-37Pb were electroplated on the comb pattern. 6.5V and 15.0V were applied in the comb pattern and then we measured the electrical short time causing by occurring the ion migration. In these results, we evaluate the sensitivity and derived the prediction models of ion migration occurrence time depending on the pattern materials, applied voltage and pattern spacing of PCB conductor.

• Journal of Mechanical Science and Technology
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• v.20 no.12
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• pp.2087-2093
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• 2006

In this paper, auto focus actuator, which is used to move a lens module in the mobile phone having a camera module, is developed. Camera module containing auto focus actuator requires to minimize total size because of characteristics of the application area such as mobile phone, digital camera, and personal digital assistant. There are stepping motor, voice coil motor, and piezoelectric motor as auto focus actuator. In this paper, voice coil motor having new electromagnetic configuration is proposed. And actuator using proposed voice coil motor is developed by optimal design method using magnetic circuit analysis. The sectional area of the developed actuator is reduced to 32.4% compared with actuator using general electromagnetic configuration. From the performance test, the developed actuator has moving stroke of 0.64 mm for 2.1 volt, hysteresis of 40 $\mu$m, full stroke current of 54 mA, and unit step motion of 3 $\mu$m.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.61 no.2
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• pp.59-66
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• 2012

Recently, the market of Electric Vehicle(EV) is increasing more and more than before. Thus a new heater for the EV is required. The PTC devices may be used the heater for the EV. In this paper, a simple DC-DC Converter is proposed as the PTC Heater for the EV. The proposed circuit was optimally desired to decrease the stress of the power devices and reduce the current ripples. To apply the result of the test in the laboratory to the actual EV system with the high DC voltage, ripple current, average current and output peak current are predicted by using the least-squares method. Finally, the proposed circuit is validated by various experiments.

• Proceedings of the KSME Conference
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• 2007.05a
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• pp.1712-1717
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• 2007

This paper presents a derating design approach for reliability improvement of an aluminum electrolytic capacitor. The capacitor, usually mounted in a printed circuit board, is used to stabilize the circuit. The main failure mechanism of interest is dry-up of the electrolyte that is mainly caused by two stresses-temperature and voltage. The lifetime under these stresses is modeled as a function of these stresses and time using accelerated life testing. Quantitative variation in the lifetime, according to variations in these stresses, is investigated to perform the derating design of the capacitor so that the stress levels are selected to achieve required reliability measures for reliability improvement. Moreover, sensitivity analysis shows which stress would be a more important factor determining the lifetime.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.878-881
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• 2001

In this paper, we analyzed the characteristics of insulating material with ELB(earth leakage circuit breaker) through tracking experiment and the study was carried out three different types of samples. The tracking is breakdown phenomenon of material surface that is generated on the organic insulating material. The test method applied IEC publication 587. The result of the sample breakdown by tracking was carbonized and resistance of between the electrodes is approximately 300$\Omega$. In the result of DSC analysis, the caloric peak was detected before 100$^{\circ}C$ in product of tracking. It appeared weight loss of 10.87% at 537$^{\circ}C$ on TGA. IR spectrum analysis showed carbon-hydrogen(C-H)bond on molecular structure that is the sample of tracking.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1993.11a
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• pp.35-38
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• 1993

SCLD(supercondocting current 1imiting device) with YBaCuO superconductor was fabricated by the sol-gel and the doctor-blade method. Critical current density ($J_{c}$) and critical current ($I_{c}$) of the SCLD are 100.27 A/$cm^2$and 1A at 77K and the electrodes contact with SCLD by silver paste. The SCL was connected with test circuit in series. When apple iud current exceed critical current value of the SCLD in testing circuit, the SCLD ristricts the over current by generating resistance itself without delay. Resistance of SCLD increase lineary 0 to 1.6$\Omega$ in propotion to applied current above the critical current $I_{c}$.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.817-820
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• 2005

Dead-Time is necessary to prevent the shot circuit of the full bridge inverters in pulse width modulation. However the output voltage deviations is the result of the Dead-Time that decrease power from the out put voltage inverters. This paper presents the method that compensate power output voltage inverters loss in Dead-Time circuit for DC Motor Drives with full bridge voltage inverters. The compensation of Dead-Time method is a sample and a low-cost solution. The comparison between the test results and simulation by MATLAB&SIMULINK under the same condition is similar.