• Journal of Applied Reliability
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• v.18 no.3
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• pp.229-239
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• 2018

Purpose: There is a difficulty in Environmental Stress Screening (ESS) test design for weapon system's electrical/electronic components/products in small and medium-sized enterprises. To overcome this difficulty, I propose an easy ESS test design approach algorithm that is optimized with only one environment tolerance design information parameter (${\Delta}T$). Methods: To propose the mass production weapon system ESS test design for cost-effective optimization, I define an optimum cost-effective mathematical model ESS test algorithm model based on modified MIL-HDBK-344, MIL-HDBK-2164 and DTIC Technical Report 2477. Results: I clearly confirmed and obtained the quantitative data of ESS effectiveness and cost optimization along our ESS test design algorithm through the practical case. I will expect that proposed ESS test method is used for ESS process improvement activity and cost cutting of mass production weapon system manufacturing cost in small and medium-sized enterprises. Conclusion: In order to compare the effectiveness of the proposed algorithm, I compared the effectiveness of the existing ESS test and the proposed algorithm ESS test based on the existing weapon system circuit card assembly for signal processing. As a result of the comparison, it was confirmed that the test time was reduced from 573.0 minutes to 517.2minutes (9.74% less than existing test time).

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.61 no.4
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• pp.199-205
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• 2012

This paper propose a improved parameter estimations of five-phase squirrel-cage induction motor(IM) for speed control system on field oriented control(FOC). In order to high performance control of ac the motors using a FOC and DTC(direct torque control) algorithm, there are required precise motor parameters for slip calculation, flux observer, controller gain, rotor position and speed estimation, and so on. We are suggest a estimation method of the motor parameters that developing five-phase squirrel-cage IM have a stator of concentrated winding for experimental. There are results of stator winding test, no-load test, locked rotor test, and obtained equivalent circuits using manufactured experimental apparatus. For presenting the superior performance of the speed control system in adapted the parameters, experimental results are presented using a 32-bit fixed point TMS320F2812 DSP with 1.5[KW] IM.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.176-186
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• 1996

As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently, IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. In this paper, G-ATPG (gyeongsang automatic test pattern genrator) is designed which is able to be adapted to IDDQ testing for combinational CMOS VLSI. In G-ATPG, stuck-at, transistor stuck-on, GOS (gate oxide short)or bridging faults which can occur within priitive gate or XOR is modelled to primitive fault patterns and the concept of a fault-sensitizing gate is used to simulate only gates that need to sensitize the faulty gate because IDDQ test does not require the process of fault propagation. Primitive fault patterns are graded to reduce CPU time for the gates in a circuit whenever a test pattern is generated. the simulation results in bench mark circuits show that CPU time and fault coverage are enhanced more than the conventional ATPG using IDDQ test.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.320-330
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• 2012

In this paper, we investigate the power integrity of grid structures for power and ground distribution on printed circuit board (PCB). We propose the 2D transmission line method (TLM)-based model for efficient frequency-dependent impedance characterization and PCB-package-integrated circuit (IC) co-simulation. The model includes an equivalent circuit model of fringing capacitance and probing ports. The accuracy of the proposed grid model is verified with test structure measurements and 3D electromagnetic (EM) simulations. If the grid structures replace the plane structures in PCBs, they should provide effective shielding of the electromagnetic interference in mobile systems. An analytical model to predict the shielding effectiveness (SE) of the grid structures is proposed and verified with EM simulations.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.10
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• pp.1286-1291
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• 2018

In recent years, the proliferation of DER (distributed energy resources) is progressing rapidly. In particular, research on LVDC distribution grid with various advantages has begun. In order to commercialize this LVDC grid, direct current protection method should be established by analysis of DC faults. Recently, the development of HSCB (high-speed circuit breaker) for new ${\pm}750[V]$ LVDC grid has been researched. This paper deals with the calculation of the maximum short-circuit fault current of the HSCB as a part of the development of HSCB for the LVDC distribution grid. First, modeling using PSCAD was carried out for PV array with BESS on the Gochang Power Test Center system. Next, to calculate the rated capacity of HSCB, fault currents were calculated and the characteristics were analyzed through fault simulations. Thus, this study results can help to establish short-circuit capacity calculation of HSCB and protection plan for DC protection relay system.

• Proceedings of the KSME Conference
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• 2007.05a
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• pp.321-325
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• 2007

Recently, demands on thin multi-layer printed circuit boards(PCB) have been rapidly increased with broad spread of personal portable digital appliances such as multi-media. In case of mobile phone, however, the fact that PCBs have low flexural strength might cause defects. The purpose of this study is to improve the flexural strength by substituting the well-known GFRP(glass fiber reinforced plastic) for CFRP(carbon fiber reinforced plastic). Firstly, finite element simulation was carried out using ABAQUS to find out a unique CFRP layer that has a role to sustain the applied forces mainly in PCB. Secondly, three point bending tests were conducted with the newly designed CFRP PCB model to verify the improvement of the flexural strength. Consequently, it is shown that PCB layered with the CFRP on both outer sides of the board can be used to improve the flexural strength effectively.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.3
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• pp.31-39
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• 2001

In this paper, we proposed a new pixel circuit of the CMOS image sensor for high dynamic range operation, which is based on a multiple sampling scheme and a conditional reset circuit. To expand the pixel dynamic range, the output is multiple-sampled in the integration time. In each sampling, the pixel output is compared with a reference voltage, and the result of comparison may activate the conditional reset circuit. The times of conditional reset, N, during the integration will contribute to the increase of the dynamic range by the times of N. The test chip was fabricated with 0.65-${\mu}m$ CMOS technology (2-P, 2-M).

• Journal of Electrical Engineering and Technology
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• v.13 no.4
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• pp.1759-1768
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• 2018

The energy density, power density and ohm resistance of battery change significantly as results of battery aging, which lead to decrease in the accuracy of the equivalent model. A parameter identification method of the equivale6nt circuit model with 3 R-C branches based on the test database of battery life cycle is proposed in this paper. This database is built on the basis of experiments such as updating of available capacity, charging and discharging tests at different rates and relaxation characteristics tests. It can realize regular update and calibration of key parameters like SOH, so as to ensure the reliability of parameters identified. Taking SOH, SOC and T as independent variables, lookup table method is adopted to set initial value for the parameter matrix. Meanwhile, in order to ensure the validity of the model, the least square method based on variable forgetting factor is adopted for optimizing to complete the identification of equivalent model parameters. By comparing the simulation data with measured data for charging and discharging experiments of Li-ion battery, the effectiveness of the full life cycle database and the model are verified.

• Progress in Superconductivity and Cryogenics
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• v.20 no.4
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• pp.16-19
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• 2018

This paper presents analytical and numerical simulation approaches on charging characteristics of no-insulation (NI) REBCO pancake coil by using the equivalent circuit model to estimate magnetic performance response in the coil. The analytical methods provide closed form or definite solution in the form of complete mathematical expressions but they are hard to solve the complex problems. Numerical methods have become popular with the development of the computing capabilities to solve the problems which are impossible or very hard to solve analytically. First of all, the equivalent circuit model are proposed to develop the simulation code for both analytical and numerical method. The charging test was performed under critical current to obtain magnetic field induced and terminal voltage through the radial as well as spiral current paths within the coil. To verify the validity of both proposed methods, the simulation results were compared and discussed with the experimental results.

• ETRI Journal
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• v.46 no.3
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• pp.550-563
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• 2024

A novel inductance simulation circuit employing only two dual-output voltage-differencing buffered amplifiers (DO-VDBAs) and a single capacitance (grounded) is proposed in this paper. The reported configuration is a purely resistor-less realization that provides electronically controllable realized inductance through biasing quantities of DO-VDBAs and does not rely on any constraints related to matched values of parameters. This structure exhibits excellent behavior under the influence of tracking errors in DO-VDBAs and does not exhibit instability at high frequencies. The simple and compact metal-oxide semiconductor (MOS) implementation of the DO-VDBAs (eight MOS per DO-VDBA) and adoption of grounded capacitance make the proposed circuit suitable for on-chip realization from the perspective of chip area consumption. The function of the pure grounded inductance is validated through high pass/bandpass filtering applications. To test the proposed design, simulations were performed in the PSPICE environment. Experimental validation was also conducted using the integrated circuit CA3080 and operational amplifier LF-356.