• Proceedings of the KIEE Conference
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• 2002.07a
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• pp.169-171
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• 2002

The western route of KEPCO's 765kV transmission line has been tentatively operating as 345kV voltage before commercial operation. After finishing the test operation of 765kV substation in 2002. KEPCO decided to operate the 765kV line for commercial operation. During the applying of 765kV voltage to the transmission line, double circuit transmission line will be operated with two voltage grades of 765kV and 345kV. Because the earthing switch is installed on both end of transmission line, we had estimated the electrostatic induction voltage and electromagnetic induction current before the line energizing in order to confirm the ratings of earthing switch. The induced voltage and current is very important for the maintenance of parallel circuit. This paper describes the simulation study of electrical phenomena such as electrostatic induction voltage from the parallel line and electromagnetic induction current from the parallel circuit. The transmission line model was developed by EMTP (Electro-Magnetic Transient Program).

• Progress in Superconductivity and Cryogenics
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• v.6 no.2
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• pp.25-28
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• 2004

Three-phase inductive superconducting fault current limiter (SFCL) with DC reactor rated on 6.6 $KV_{rms}/200 A_{rms}$ has been developed in Korea. This system consists of one DC reactor, AC/DC power converter, and a three-phase transformer, which is called magnetic core reactor (MCR). This paper deals with the short-circuit analysis of the SFCL. The DC reactor was the HTS solenoid coil whose inductance was 84mH. The power converter was performed as the dual-mode operation for dividing voltage between the rectifying devices. The short-term normal operation (1 see) and short-circuit tests (2∼3 cycles) of this SFCL were performed successfully. In regular short-circuit test, the fault current was limited as 30% of rated short-circuit current at 2 cycles after the fault. The experimental results have a very similar tendency to the simulation results. Using the technique for the fault detection and SCR firing control, the fault current limiting rate of the SFCL was improved. From this research, the parameters for design and manufacture of large-scale SFCL were obtained.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.72-79
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• 2003

Due to the improvements in circuit design technique and manufacturing technique, complexity of a circuit is growing along with the demand for memories with large capacities. Likewise, as a memory capacity gets larger, testing gets harder and testing cost increases, and testing process in chip development gets larger as well. Therefore, a research on an effective test algorithm to improve the chip yield rate in a short time period is becoming an important task. This paper proposes an effective, March C-algorithm based, test algorithm that can also be applied to a dual-port memory since it considers all the fault types, which can be occurred in a single-port as well as in a dual-port memory, without increasing the test length.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.633-634
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• 2006

A new specification-based analog and mixed-signal test technique using high performance current sensors is proposed. The proposed technique using current sensors built in external ATE has little hardware overhead in circuit under test and high testability without time consuming operation of test point placement algorithm.

• Progress in Superconductivity
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• v.6 no.2
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• pp.104-107
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• 2005

We have developed and tested an RSFQ 4-bit Arithmetic Logic Unit (ALU) based on half adder cells and de switches. ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We have simulated the circuit by using Josephson circuit simulation tools in order to reduce the timing problem, and confirmed the correct operation of the designed ALU. We used simulation tools of $XIC^{TM},\;WRspice^{TM}$, and Julia. The fabricated 4-bit ALU circuit had a size of $\3000{\ cal}um{\times}1500{\cal}$, and the chip size was $5{\cal} mm{\times}5{\cal}mm$. The test speeds were 1000 kHz and 5 GHz. For high-speed test, we used an eye-diagram technique. Our 4-bit ALU operated correctly up to 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

• Journal of Korean Clinical Nursing Research
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• v.17 no.2
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• pp.192-203
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• 2011

Purpose: The purpose of this study was to compare the body temperature (BT), blood pressure (BP) and shivering in patients undergoing operation under general anesthesia between the heated humidification circuit tube (HHCT) group and the non-HHCT group. Methods: Data were extracted from the participants' medical records from September 1st to December 30th, 2009. The HHCT group consisted of 50 cases who were applied with heated and humidified gas via a specially designed circuit under general anesthesia. The HHCT which was adjusted at $41^{\circ}C$ was applied from induction of general anesthesia to extubation. In comparison, the non-HHCT group consisted of 50 cases who were applied with gas through standard breathing circuit without heat and humidification. Collected data were analyzed by $x^2$ test, t-test and repeated measures ANOVA. Results: The BT and shivering were significantly different between two groups (p<.001). But the BP was was not signigicantly different between the HHCT group and the non-HHCT group. Conclusion: The application of heated and humidified gases to patients under general anesthesia was effective in preserving the body temperature and reducing the shivering.

• Journal of The Korean Society of Integrative Medicine
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• v.9 no.4
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• pp.211-223
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• 2021

Purpose : The purpose of this study was to examine the effect of task-oriented circuit training using unstable support surface on balance, gait ability, and balance confidence in subacute stroke patients. Methods : Forty-five patients with subacute stroke were randomly divided into the three following groups of 15: 1) TOCT-US group; task-oriented circuit training using unstable surface (experimental group 1), 2) TOCT-SS group; task-oriented circuit training using stable surface (experimental group 2), and 3) CON group; conventional physical therapy (control group). All patients participated in one of the three training programs for 6 weeks, 30 minutes per session, 3 times per week. Patients' balance ability was assessed using the BT-4, BBS (berg balance scale), TUG (time up and go test), and LOS (limit of stability). Gait speed was measured to examine gait ability. K-ABC (activities-specific balance confidence scale) was also used to assess the level of patients' confidence in daily activities. Results : After the intervention, the sway area in experimental groups 1 and 2 decreased, but that in the control group increased. Experimental group 1 showed significant improvement compared with experimental group 2 and the control group. BBS, TUG, and LOS scores of experimental group 1 were significantly improved compared with those of experimental group 2 and the control group. Also, gait speed significantly improved in experimental group 1 compared with experimental group 2 and the control group. Experimental groups 1 and 2 showed significant improvement in K-ABC scores after training. Conclusion : Patients with subacute stroke had significantly improved balance, gait, and level of confidence in performing activities of daily living following task-oriented circuit training using the unstable surface. This indicates that task-oriented circuit training using unstable surfaces can be an effective treatment method for the recovery of balance and gait in subacute stroke patients.

• Journal of Electrical Engineering and Technology
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• v.1 no.3
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• pp.359-365
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• 2006

Since the start of the KSTAR (Korea Superconducting Tokamak Advanced Research) project, Instrumentation and Control (I&C) of the Neutral Beam Test Facility (NB-TF) has been striving to answer diverse requests arising from various facets during the project's development and construction phases. Hard-wired electrical circuits have been designed, tested, fabricated, and finally installed to the relevant parts of the system. In relation to the vacuum system I&C, controlling functions for the rotary pumps, a Roots pump, two turbomolecular pumps, and four cryosorption pumps have been constructed. I&C for the ion source operation are the temperature and flow rate signal monitoring, Langmuir probe signal measurements, gradient grid current measurements, and arc detector circuit. For the huge power system to be monitored or safely operated, many temperature measurement functions have also been implemented for the beam line components like the neutralizer, bending magnet, ion dump, and calorimeter. Nearly all of the control and probe signals between the NB test stand and the control room were made to be transmitted through the optical cables. Failures of coolant flow or beam line vacuum pressure were made to be safely blocked from influencing the system by an appropriate interlock circuit that will shut down the extraction voltage application to the system or prevent damages to the vacuum components. Preliminary estimation of the beam power through the calorimetric measurement shows that 87.9% of the total power of the 60kV/18A beam with 200 seconds duration is absorbed by the calorimeter surface. Most of these I&C results would be highly appropriate for the construction of the main NBI facility for the KSTAR national fusion research project.

• Proceedings of the KIEE Conference
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• 1999.11d
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• pp.978-980
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• 1999

In this paper, DC degradation of ZnO varistor sintered in the atmospheres of nitrogen and oxygen was investigated. The content of $SiO_2$ containing 0.0, 0.2, 0.5 mol% respectively was addicted for the improvement of degradation property. ZnO varistor was fabricated in the special electrical furnace which had the vacuum system. The temperature and the voltage for the DC degradation test were $115{\pm}2^{\circ}C$, $0.85V_{1mA/cm^2}$. The time conditions for this test were 0, 2, 4, 8 hours and Current-voltage analysis is used to determine nonlinear coefficients($\alpha$). Frequency analysis are accomplished for the understanding of electrical properties as DC degradation test. In this experiment, We concluded that nonlinear coefficient decreased as the amount of $SiO_2$ addition increased, but degradation rate coefficient increased as the amount of $SiO_2$ addition increased. Also, degradation test with the analysis of equivalent circuit showed that the degradation phenomenon of ZnO varistor wasn't linearity.

• Korean Journal of Materials Research
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• v.15 no.1
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• pp.54-60
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• 2005

Recently a lots of problems have observed in high densified and high integrated electronic components. One of them is ion migration phenomena, which induce the electrical short of electrical circuit. ion migration phenomena has been observed in the field of exposing the specific environment and using for a long tin e. This study was evaluated the generation time of ion migration and was investigated properly test method through water drop test and high temperature high humidity test. Also we observed direct causes and confirmed generation mechanism of dendritic growth as we reproduced the ion migration phenomena. We utilized PCB(printed circuit board) having a comb pattern as follows 0.5, 1.0, 2.0 mm pattern distance. Cu, SnPb and Au were electroplated on the comb pattern. 6.5 V and 15 V were applied in the comb pattern and then we measured the electrical short time causing by ion migration. In these results, we examined a difference of ion migration time depending on pattern materials, applied voltage and pattern spacing of PCB conductor.