• Journal of Advanced Navigation Technology
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• v.17 no.5
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• pp.560-567
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• 2013

In this paper, it is proposed the fault detection method of the ASIC, without the Test Requirement Document(TRD), extracting internal logic circuit and analyzed the function of the ASIC using the multipurpose development program and simulation. If there don't have the TRD, it is impossible to analyze the operation of the circuit and find out the fault detection in any chip. Therefore, we make the TRD based on the analyzed logic data of the ASIC, and diagnose of the ASIC circuit at the gate level through the signal control of I/O pins using the Dynamic Pattern signal. According to the experimental results of the proposed method, we is confirmed the good performance of the fault detection capabilities which applied to the non-memory circuit.

• Journal of International Academy of Physical Therapy Research
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• v.3 no.1
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• pp.370-377
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• 2012

This study examines the effects of different environments on the application of hemiplegia patients circuit balance training. Group 1 performed circuit balance training without any auditory intervention Group 2 performed training in noiseless environments and Group 3 performed training in white noise environments. First, among lower extremity muscular strength evaluation items, maximum activity time(MAT) was not significantly different(p>.05). Maximum muscle strength(MMS) increased significantly in Group 3(p<.01), there was no significant difference in MMS among the groups. Average muscle strength(AMS) indexes also significantly increased in Group 3(p<.01), there was no significant difference in AMS among the groups. Second, among balancing ability evaluation items, Berg's balance scale(BBS) scores significantly increased in all groups(p<.05), BBS scores were significantly difference among the groups. Based on the results, Group 1, 2 and Group 1, 3 showed significant increases (p<.05). Functional reach test(FRT) values significantly increased in Group 2, 3(p<.05), and there was no significant difference in FRT values among the groups. Timed up and go(TUG) test values significantly decreased in Group 2, 3(p<.05), and there was no significant difference in TUG test values among the groups. Third, among walking speed evaluation items, the time required to walk 10m significantly decreased in all groups(p<.05), and there was no significant difference in the values among the groups. Average walking speeds showed significant increases in Group 1, 3(p<.05), and there was no significant difference in the values among the groups. Based on the results of this study, noise environments should be improved by either considering auditory interventions and noiseless environments, or by ensuring that white noise environments facilitate the enhancement of balancing ability.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.3
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• pp.275-278
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• 2008

It has been issued that the necessity of Live line work for 765kV vertical double circuit six bundle conductors transmission line when the characteristics of transmission line, the composition of T/L and near the T/L circumstances etc. Others are considered. The Barehand method of UHV T/L is extremely dangerous work and especially it is directly related with lineman life so it is very dangerous. It should be performed several technology developments for live-line work on the UHV T/L, that should be considered such as the electrical influence on workers near the T/L, development of live-line facilities, guarantee of safety, the technical rules of live-line work, the safe method of live-line work and etc. In order to maintain the 765kV transmission lines safely by barehand work, first of all, we should know the analysis of electrical safety level test in live-line work at 765kV vertical double circuit six bundle conductors on the suspension string tower type.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.396-397
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• 2015

With the increasing utilization of high-voltage, direct current (HVDC) transmissions in modern power systems, the DC grid is becoming a hot topic in academic and practical systems. In the DC grid, one of the urgent problems is the fast clearance of the DC fault in the DC network. One preferred method is to isolate the faulty point from the DC network in a short time. The DC circuit breaker is to interrupt the overcurrent after DC faults occur. In this paper, a self-excited resonant DC circuit breaker is an easy and cheap equipment to interrupt the DC fault current. The Mayr's arc model is utilized to simulate the self-excited DC circuit breaker in a DC test system in PSCAD/EMTDC.

• Corrosion Science and Technology
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• v.7 no.1
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• pp.61-67
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• 2008

In this paper, electrochemical and microstructural characteristics of nickel-plated Alloy 600 were investigated in order to identify the performance of electroless Ni-plating on Alloy 600 in high-temperature aqueous condition with the comparison of electrolytic nickel-plating. For high temperature corrosion test of nickel-plated Alloy 600, specimens were exposed for 770 hours to typical PWR primary water condition. During the test, open circuit potentials (OCP's) of all specimens were measured using a reference electrode. Also, resistance to flow accelerated corrosion (FAC) test was examined in order to check the durability of plated layers in high-velocity flow environment at high temperature. After exposures to high flow rate aqueous condition, the integrity of surfaces was confirmed by using both scanning electron microscopy (SEM) and energy dispersive spectroscopy (EDS). For the field application, a remote process for electroless nickel-plating was demonstrated using a plate specimen with narrow gap on a laboratory scale. Finally, a practical seal design was suggested for more convenient application.

• Transactions on Electrical and Electronic Materials
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• v.5 no.1
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• pp.19-23
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• 2004

A novel method of high speed, accurate circuit simulation in 3-dimensional (3-D) parallel-plate capacitors is investigated. The basic concept of the circuit simulation methods is partial element equivalent circuit model. The three test structures of 3-D parallel-plate capacitors are fabricated by using multi-layer low-temperature co-fired ceramic (LTCC) process and their S-parameters are measured between 50 MHz and 5 GHz. S-parameters are converted to Y-parameters, for comparing measured data with simulated data. The circuit model parameters of the each building block are optimized and extracted using HSPICE circuit simulator. This method is convenient and accurate so that circuit design applications can be easily manipulated.

• Journal of the Korea Society of Computer and Information
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• v.3 no.2
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• pp.69-76
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• 1998

To test all internal faults in the case that the number of Primary Input is N, we need patterns that are composed of PI's of maximum 2N. In this paper, we proposed the method to reduce a search space by dividing the multiple output circuit into subcircuit that is related with output. And this method, called PBM(Partition-Based Method), can generate a set of test pattern. The method can effectively generate a test pattern for evaluating all fault of circuit, because the length of input pattern is smaller than that of full circuit and PBM doesn't search any signal line that is not concerned with detecting fault.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.401-410
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• 2017

In this work, we show that the excessive lattice heating problem due to parasitic pnp transistor action in the diode electrostatic discharge (ESD) protection device in the diode input protection circuit, which is favorably used in CMOS RF ICs, can be solved by adopting a symmetrical cathode structure. To explain how the recipe works, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixed-mode transient simulations utilizing a 2-dimensional device simulator. We attempt an in-depth comparison study by varying device structures to suggest valuable design guidelines in designing the protection diodes connected to the $V_{DD}$ and $V_{SS}$ buses. Even though this work is based on mixed-mode simulations utilizing device and circuit simulators, the analysis given in this work clearly explain the mechanism involved, which cannot be done by measurements.

• Journal of Applied Reliability
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• v.12 no.3
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• pp.153-163
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• 2012

Recently, as a electronic components are becoming more high-density, so that electronic circuits have smaller pitches between the leads and are more vulnerable to insulation failure. And the reliability of electric insulation has become an ever important issue as device contact pitches and print patterns shrink. Ion migration occurs in highly humid environment as voltage is applied to an installed print circuit. Under highly humid and voltage applied circumstances, electronic components respond to applied voltages by electrochemical ionization of metals, and a conducting filament forms between the anode and cathode across a nonmetallic medium. This leads to short-circuit failure of the electronic component. In thesis, we study acceleration test of ion migration in FR-4 PCB plated with Sn. Voltage applied test of FR-4 PCB circuits plated with Sn was tested in the temperature and humidity environments. As a result of this test, equation of acceleration model was derived.

• Journal of Electrical Engineering and Technology
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• v.3 no.1
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• pp.130-134
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• 2008

The increasing size of very large scale integration (VLSI) circuits, high transistor density, and popularity of low-power circuit and system design are making the minimization of power dissipation an important issue in VLSI design. Test Power dissipation is exceedingly high in scan based environments wherein scan chain transitions during the shift of test data further reflect into significant levels of circuit switching unnecessarily. Scan chain or cell modification lead to reduced dissipations of power. The ETC algorithm of previous work has weak points. Taking all of this into account, we therefore propose a new algorithm. Its name is RE_ETC. The proposed modifications in the scan chain consist of Exclusive-OR gate insertion and scan cell reordering, leading to significant power reductions with absolutely no area or performance penalty whatsoever. Experimental results confirm the considerable reductions in scan chain transitions. We show that modified scan cell has the improvement of test efficiency and power dissipations.