• Proceedings of the KSME Conference
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• 2001.06a
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• pp.945-950
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• 2001

Vacuum interrupters that is used in various switchgear components such as circuit breakers, distribution switches, contactors, etc. spreads the arc uniformly over the surface of the contacts. The electrode of vacuum interrupters is used sintered Cu-Cr material satisfied with good electrical and mechanical characteristics. Because the closing velocity is 1-3m/s, the deformation of the material of electrodes depends on the strain rate and the dynamic behavior of the sintered Cu-Cr material is a key to investigate the impact characteristics of the electrodes. The dynamic response of the material at the high strain-rate is obtained from the split Hopkinson pressure bar test using cylinder type specimens. Experimental results from both quasi-static and dynamic compressive tests with the split Hopkinson pressure bar apparatus are interpolated to construct the Johnson-Cook equation as the constitutive relation that should be applied to simulation of the dynamic behavior of electrodes. To evaluate impact characteristic of a vacuum interrupter, simulation is carried out with five parameters such as initial velocity, added mass of a movable electrode, wipe spring constant, initial offset of a wipe spring and virtual fixed spring constant.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.2
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• pp.135-140
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• 2008

In this paper, the spiral antenna with the center frequencies of 315MHz, 433MHz, and 447MHz for RKE system of a vehicle is designed on PCB. The antenna is microstrip line-fed, and applied PIFA concept near the feeding part to easily tune center frequency and input impedance. The PIFA-type spiral antenna with the size of $30mm{\times}20mm$ is designed on printed PCB by considering the effect of circuits and components on PCB, ECU case and vehicle body. Also chip inductor inserted dual-band spiral antenna of 315MHz and 447MHz is designed. We found that the antenna designed on PCB satisfied the antenna specifications through measurement and field test.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.34 no.6
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• pp.42-50
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• 2006

This paper addresses the optimized thermal modeling methodology for spacecraft board level thermal analysis. A direct thermal modeling of external and internal structure of active parts which have high power dissipation is newly proposed, based on conventional plate modeling for Printed Circuit Board(PCB). The parts thermal modeling results were compared with other generic methodologies and verified by thermal vacuum test. This parts thermal modeling was directly applied to thermal analysis of CS(Communication Subsystem) board of HAUSAT-2 small satellite. As a result, it was confirmed that the parts thermal modeling can complement other conventional modeling methodologies. A parts thermal modeling is very effective for thermal control design, since the existing thermal problems can be solved at the parts level in advance.

• Transactions on Electrical and Electronic Materials
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• v.5 no.2
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• pp.71-75
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• 2004

This paper proposes a new bandgap reference (BGR) circuit which takes advantage of a cascode current mirror biasing to reduce the V$\_$ref/ variation, and sizing technique, which utilizes two related ratio numbers k and N, to reduce the PNP BJT area. The proposed BGR is designed and fabricated on a test chip with a goal to provide a reference voltage to the 10 bit A/D(4-4-4 pipeline architecture) converter of the CMOS Active Pixel Sensor (APS) imager to be used in X-ray imaging. The basic temperature variation effect on V$\_$ref/ of the BGR has a maximum delta of 6 mV over the temperature range of 25$^{\circ}C$ to 70$^{\circ}C$. To verify that the proposed BGR has radiation hardness for the X-ray imaging application, total ionization dose (TID) effect under Co-60 exposure conditions has been evaluated. The measured V$\_$ref/ variation under the radiation condition has a maximum delta of 33 mV over the range of 0 krad to 100 krad. For the given voltage, temperature, and radiation, the BGR has been satisfied well within the requirement of the target 10 bit A/D converter.

• Proceedings of the KIEE Conference
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• 1998.07f
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• pp.2067-2069
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• 1998

A prototype semiconductor switch for the command resonant charging system has been developed for a line type modulator, which charges parallel pulse forming network(PFN) up to voltage of 5 kV at repetition rates of 60 Hz. A phase controlled power supply provides charging of the 4.7 ${\mu}s$ filter capacitor bank to voltage up to 5 kV. A solid state module of series stack array of sixe matched SCRs(1.6 kV, 50 A) is used as a command charging switch to initiate the resonant charging cycle. Both resistive and RC snubber network are used across each stage of the switch assembly in order to ensure proper voltage division during both steady state and transient condition. A master trigger signal is generated to trigger circuits which are transmitted through pulse transformer to each of the 6 series switch stages. A pulse transformer is required for high voltage trigger or power isolation. This paper will discuss trigger method, protection scheme, circuit simulation, and test result.

• Proceedings of the IEEK Conference
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• summer
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• pp.199-203
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• 2004

In this paper, we only describe the digital block of two-channel 18-bit analog-to-digital (A/D) converter employing sigma-delta method and xl28 decimation. The device contains two fourth comb filters with 1-bit input from sigma­delta modulator. each followed by a digital half band FIR(Finite Impulse Response) filters. The external analog sigma-delta modulators are sampled at 6.144MHz and the digital words are output at 48kHz. The fourth-order comb filter has designed 3 types of ways for optimal power consumption and signal-to-noise ratio. The following 3 digital filters are designed with 12tap, 22tap and 116tap to meet the specification. These filters eliminate images of the base band audio signal that exist at multiples of the input sample rate. We also designed these filters with 8bit and 16bit filter coefficient to analysis signal-to-noise ratio and hardware complexity. It also included digital output interface block for I2S serial data protocol, test circuit and internal input vector generator. It is fabricated with 0.35um HYNIX standard CMOS cell library with 3.3V supply voltage and the chip size is 2000um by 2000um. The function and the performance have been verified using Verilog XL logic simulator and Matlab tool.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.04a
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• pp.27-34
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• 2001

The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.38-46
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• 2006

A parallel analog Viterbi decoder which decodes PRML signal of DVD has been fabricated into a VLSI chip. The parallel analog Viterbi decoder implements the functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. In this paper, the analog parallel Viterbi decoding technology is applied for the PRML signal decoding of DVD. The benefits are low power consumption and less silicon consumption. The designed circuits are analysed and the test results of the fabricated chip are reported.

• Journal of Drive and Control
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• v.15 no.2
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• pp.1-8
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• 2018

This study is a first step toward reducing surge pressure, and it has another purpose, which is to developing an analysis model which can closely analyze a hydraulic circuit and be used in design. For development of analysis model, SimulationX, a commercial program, is used. The study progress methods are as follows. By analyzing the structure and operating mechanisms of each part of the hydraulic system of the pump truck and referring its parameters, develop a single component model. Assemble the developed single component model, and make an overall analysis the model. By comparing the similarities between the developed model and the actual system's test results, validate the reliability of the analysis model.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3181-3183
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• 1999

A CMOS two-stage oscillator applicable to requiring in- and quadrature-phase components such as RF and data retiming applications are presented using phase-look-ahead technique. This paper clearly describes the operation principle of the presented two-stage oscillator and the principle can be also applicable to the high speed high speed divide-by-two is usually used for prescaler of the frequency synthesizer. Also, the sucessful oscillation of the proposed oscillator using PLA is confirmed through the experiment. The test vehicle is designed using 0.8 ${\mu}m$ N-well CMOS process and it has a maximum 914MHz oscillation showing -75dBclHz phase noise at 100kHz offset with single 2V supply.