• Title/Summary/Keyword: implementation algorithm

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Design and Implementation of a Hybrid Spatial Reasoning Algorithm (혼합 공간 추론 알고리즘의 설계 및 구현)

  • Nam, Sangha;Kim, Incheol
    • Journal of KIISE
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    • v.42 no.5
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    • pp.601-608
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    • 2015
  • In order to answer questions successfully on behalf of the human contestant in DeepQA environments such as 'Jeopardy!', the American quiz show, the computer needs to have the capability of fast temporal and spatial reasoning on a large-scale commonsense knowledge base. In this paper, we present a hybrid spatial reasoning algorithm, among various efficient spatial reasoning methods, for handling directional and topological relations. Our algorithm not only improves the query processing time while reducing unnecessary reasoning calculation, but also effectively deals with the change of spatial knowledge base, as it takes a hybrid method that combines forward and backward reasoning. Through experiments performed on the sample spatial knowledge base with the hybrid spatial reasoner of our algorithm, we demonstrated the high performance of our hybrid spatial reasoning algorithm.

IR Image Processing IP Design, Implementation and Verification For SoC Design

  • Yoon, Hee-Jin
    • Journal of the Korea Society of Computer and Information
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    • v.23 no.1
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    • pp.33-39
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    • 2018
  • In this paper, We studied the possibility of SoC(System On Chip) design using infrared image processing IP(Intellectual Property). And, we studied NUC(Non Uniformity Correction), BPR(Bad Pixel Recovery), and CEM(Contrast Enhancement) processing, the infrared image processing algorithm implemented by IP. We showed the logic and timing diagram implemented through the hardware block designed based on each algorithm. Each algorithm was coded as RTL(Register Transfer Level) using Verilog HDL(Hardware Description Language), ALTERA QUARTUS synthesis, and programed in FPGA(Field Programmable Gated Array). In addition, we have verified that the image data is processed at each algorithm without any problems by integrating the infrared image processing algorithm. Particularly, using the directly manufactured electronic board, Processor, SRAM, and FLASH are interconnected and tested and the verification result is presented so that the SoC type can be realized later. The infrared image processing IP proposed and verified in this study is expected to be of high value in the future SoC semiconductor fabrication. In addition, we have laid the basis for future application in the camera SoC industry.

Analysis of Implementation and Performance of LEA Algorithm for Server Environment (서버환경에서의 LEA 암호 알고리즘 구현 및 성능분석)

  • Yun, Chae-won;Lee, Jaehoon;Yi, Okyoen
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2014.10a
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    • pp.359-362
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    • 2014
  • With recent growing of application service, servers are required to sustain great amount of data and to handle them quickly: besides, data must be processed securely. The main security algorithm used in security services of server is AES(Advanced Encryption Standard - 2001 published by NIST), which is widely accepted in the world market for superiority of performance. In Korea, NSRI(National Security Research Institute) has developed ARIA(Academy, Research Institute, Agency) algorithm in 2004 and LEA(Lightweight Encryption Algorithm) algorithm in 2012. In this paper, we show advantage of LEA by comparing performance with AES and ARIA in various servers.

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Design and Implementation of a friendly maze program for early childhood based on a path searching algorithm

  • Yun, Unil;Yu, Eun Mi
    • Journal of the Korea Society of Computer and Information
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    • v.22 no.6
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    • pp.49-55
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    • 2017
  • Robots, games and life applications have been developed while computer areas are developed. Moreover, various applications have been utilized for various users including the early childhood. Recently, smart phones have been dramatically used by various users including early childhood. Many applications need to find a path from a starting point to destinations. For example, without using real maps, users can find the direct paths for the destinations in realtime. Specifically, path exploration in game programs is so important to have accurate results. Nowadays, with these techniques, diverse applications for educations of early childhood have been developed. To deal with the functions, necessity of efficient path search programs with high accuracy becomes much higher. In this paper, we design and develop a friendly maze program for early childhood based on a path searching algorithm. Basically, the path of lineal distance from a starting location to destination is considered. Moreover, weight values are calculated by considering heuristic weighted h(x). In our approach, A* algorithm searches the path considering weight values. Moreover, we utilize depth first search approach instead of breadth first search in order to reduce the search space. so it is proper to use A* algorithm in finding efficient paths although it is not optimized paths.

AllEC: An Implementation of Application for EC Numbers Prediction based on AEC Algorithm

  • Park, Juyeon;Park, Mingyu;Han, Sora;Kim, Jeongdong;Oh, Taejin;Lee, Hyun
    • International Journal of Advanced Culture Technology
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    • v.10 no.2
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    • pp.201-212
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    • 2022
  • With the development of sequencing technology, there is a need for technology to predict the function of the protein sequence. Enzyme Commission (EC) numbers are becoming markers that distinguish the function of the sequence. In particular, many researchers are researching various methods of predicting the EC numbers of protein sequences based on deep learning. However, as studies using various methods exist, a problem arises, in which the exact prediction result of the sequence is unknown. To solve this problem, this paper proposes an All Enzyme Commission (AEC) algorithm. The proposed AEC is an algorithm that executes various prediction methods and integrates the results when predicting sequences. This algorithm uses duplicates to give more weights when duplicate values are obtained from multiple methods. The largest value, among the final prediction result values for each method to which the weight is applied, is the final prediction result. Moreover, for the convenience of researchers, the proposed algorithm is provided through the AllEC web services. They can use the algorithms regardless of the operating systems, installation, or operating environment.

Implementation of a High-Quality Audio Collaboration System Over IP Networks (IP 네트워크 기반 고품질 오디오 협업 시스템)

  • Kang, Jin-Ah;Kim, Hong-Kook
    • 한국HCI학회:학술대회논문집
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    • 2008.02a
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    • pp.218-223
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    • 2008
  • In this paper, we implement several methods to improve an audio collaboration system over IP networks, and then evaluate the performance of the implemented methods. In general, speech and audio quality degrades depending on the characteristics of IP networks such as jitter and packet loss. In order to reduce this quality degradation, we propose a lower bit rate audio delivery scheme using the MPEG-2 AAC (Advanced Audio Coding) audio codec in a viewpoint that a packet loss rate could be reduced by a smaller packet size. In addition, iLBC (Internet Low-Bitrate Codec) and the G.711 packet loss concealment algorithm defined by IEFT and ITU-T, respectively, are applied to a audio collaboration system. RAT (Robust-Audio Tool)[7] is used as a baseline platform for the implementation of the proposed methods. It is shown from the implementation that the implemented MPEG-2 AAC audio codec with a bitrate of 256 kbit/s performs as similar as the uncompressed audio quality with a bitrate of 512 kbit/s, and that iLBC and the G.711 packet loss concealment algorithm can improve speech quality when a packet loss rate is 2~10%.

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Design and Implementation of Optical Flow Estimator for Moving Object Detection in Advanced Driver Assistance System (첨단운전자보조시스템용 이동객체검출을 위한 광학흐름추정기의 설계 및 구현)

  • Yoon, Kyung-Han;Jung, Yong-Chul;Cho, Jae-Chan;Jung, Yunho
    • Journal of Advanced Navigation Technology
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    • v.19 no.6
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    • pp.544-551
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    • 2015
  • In this paper, the design and implementation results of the optical flow estimator (OFE) for moving object detection (MOD) in advanced driver assistance system (ADAS). In the proposed design, Brox's algorithm with global optimization is considered, which shows the high performance in the vehicle environment. In addition, Cholesky factorization is applied to solve Euler-Lagrange equation in Brox's algorithm. Also, shift register bank is incorporated to reduce memory access rate. The proposed optical flow estimator was designed with Verilog-HDL, and FPGA board was used for the real-time verification. Implementation results show that the proposed optical flow estimator includes the logic slices of 40.4K, 155 DSP48s, and block memory of 11,290Kbits.

The Low Cost Implementation of Speech Recognition System for the Web (웹에서의 저가 음성인식 시스템의 구현)

  • Park, Yong-Beom;Park, Jong-Il
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.4
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    • pp.1129-1135
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    • 1999
  • isolated word recognition using the Dynamic Time warping algorithm has shown good recognition rate on speaker dependent environment. But, practically, since the searching time of the dynamic Time Warping algorithm is rapidly increased as searching data is increased. it is hard to implement. In the context-dependent-short-query system such as educational children's workbook on the Web, the number of responses to the specific questions is limited. Therefore, the searching space for the answers can be reduced depending on the questions. In this paper, low cost implementation method using DTW for the Web has been proposed. To cover the weakness of DTW, the searching space is reduced by the context. the searching space, depends on the specific questions, is chosen from interest searchable candidates. In the real implementation, the proposed method show better performance of both time and recognition rate.

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An Implementation of Authentication and Encryption of Multimedia Conference using H.235 Protocol (H.235 프로토콜에 의한 영상회의의 인증과 암호화 구현)

  • Sim, Gyu-Bok;Lee, Keon-Bae;Seong, Dong-Su
    • The KIPS Transactions:PartC
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    • v.9C no.3
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    • pp.343-350
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    • 2002
  • This paper describes the implementation of H.235 protocol for authentication and media stream encryption of multimedia conference systems. H.235 protocol is recommended by ITU-T for H.323 multimedia conference security protocol to prevent from being eavesdropped and modified by an illegal attacker. The implementation in this paper has used password-based with symmetric encryption authentication. Media streams are encrypted using the Diffie-Hellman key exchange algorithm and symmetric encryption algorithms such as RC2, DES and Triple-DES. Also, 128-bit Advanced Encryption Standard and 128-bit Korean standard SEED algorithms are implemented for the future extension. The implemented authentication and media stream encryption has shown that it is possible to identify terminal users without exposing personal information on networks and to preserve security of multimedia conference. Also, encryption delay time and used memory are not increased even though supporting media stream encryption/decryption, thus the performance of multimedia conference system has not deteriorated.

Design and Implementation of Real-time High Performance Face Detection Engine (고성능 실시간 얼굴 검출 엔진의 설계 및 구현)

  • Han, Dong-Il;Cho, Hyun-Jong;Choi, Jong-Ho;Cho, Jae-Il
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.47 no.2
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    • pp.33-44
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    • 2010
  • This paper propose the structure of real-time face detection hardware architecture for robot vision processing applications. The proposed architecture is robust against illumination changes and operates at no less than 60 frames per second. It uses Modified Census Transform to obtain face characteristics robust against illumination changes. And the AdaBoost algorithm is adopted to learn and generate the characteristics of the face data, and finally detected the face using this data. This paper describes the face detection hardware structure composed of Memory Interface, Image Scaler, MCT Generator, Candidate Detector, Confidence Comparator, Position Resizer, Data Grouper, and Detected Result Display, and verification Result of Hardware Implementation with using Virtex5 LX330 FPGA of Xilinx. Verification result with using the images from a camera showed that maximum 32 faces per one frame can be detected at the speed of maximum 149 frame per second.