• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.107-115
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• 1998

A multiplier bit-pair recoding technique derived from Booth algorithm is used as an effective method that can carry out a fast binary multiplication regardless of a sign of both multiplicand and multiplier. In this paper, we propose an implementation of an optical high-speed multiplier which consists of a symbolic substitution adder and an optical multiplication algorithm, which transforms and enhances the multiplier bit-pair recoding algorithm to be fit for optical characteristics. Specially, a symbolic substitution addition rules are coded with a dual-rail logic, and so the complement of the logic of the symbolic substitution adder is easily obtained with a shift operation because it is always present. We also construct the symbolic substitution system which makes superposition image by superimposing two shifted images in a serial connection and recognizes a reference image by feeding this superimposed image to a mask. Thus, the optical multiplier, which is compared with a typical system, is implemented to the smaller system by reducing the number of optical passive elements and the size of this system.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.6
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• pp.597-604
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• 2019

In this paper, we propose an improved method on an adaptive application of the CPP(Chinese Postman Problem) algorithm to the protocol test suite generation for conformance testing. Also, we present an example application of this CPP algorithm to B-ISDN Q.2931 call/connection control procedure for the purpose of showing how it can be adapted to generate a test suite for conformance testing of a communication protocol. The proposed method has an advantage of an optimization technique which finds a minimum cost of test suite from a standardized specification, so this optimization technique of the CPP algorithm can be practically applied to a real environment for testing a conformity of a protocol implementation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.8
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• pp.5579-5585
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• 2015

In FFT(Fast Fourier Transform) implementation, DIT(Decimation-In-Time) and DIF (Decimation-In-Frequency) methods are mostly used. Among them, various DIF structures such as Radix-2/4/8 algorithm have been developed. Compared to the DIF, the DIT structures have not been investigated even though they have a big advantage producing a sequential output. In this paper, a butterfly structure for DIT Radix-8 algorithm is proposed. The proposed structure has smaller latency time because of Radix-8 algorithm in addition to the advantage of the sequential output. In case of 4096-point FFT implementation, the proposed structure has only 4 stages which shows the smaller latency time compared to the 12 stages of Radix-2 algorithm. The proposed butterfly can be used in FFT block required the sequential output and smaller latency time.

• Journal of the Korea Society of Computer and Information
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• v.11 no.2 s.40
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• pp.159-167
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• 2006

Lipreading has been suggested as one of the methods to improve the performance of speech recognition in noisy environment. However, existing methods are developed and implemented only in software. This paper suggests a hardware design for real-time lipreading. For real-time processing and feasible implementation, we decompose the lipreading system into three parts; image acquisition module, feature vector extraction module, and recognition module. Image acquisition module capture input image by using CMOS image sensor. The feature vector extraction module extracts feature vector from the input image by using parallel block matching algorithm. The parallel block matching algorithm is coded and simulated for FPGA circuit. Recognition module uses HMM based recognition algorithm. The recognition algorithm is coded and simulated by using DSP chip. The simulation results show that a real-time lipreading system can be implemented in hardware.

• The Transactions of the Korea Information Processing Society
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• v.3 no.6
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• pp.1483-1492
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• 1996

In this paper, related on the postal business with the GIS(Geographics Information System), it discusses design and implementation of the PROS(Postal Route Optimization System) model and its main module, the shortest path generation algorithm, for supporting to postal route managements. It explains examples requirements of postal route system, and suggests the efficient PROS model using our developed shortest path generation algorithm. Because the shortest path algorithm adopts not only consider the Dijkstra algorithm of graph theory, but also the method with the direction property, PROS can be implemented with fast and efficient route search. PROS is mainly constituted of the Shortest Generator, the Isochronal Area Generator, and the Path Rearrangement Generator. It also exploits the GIS engine and the spatial DBMS (Data Base Management System) for processing coordinates in the map and geographical features. PROS can be used in the management of postal delivery business and delivery area and route, and in the rearrangement of route. In the near future, it can be also applied to commercial delivery businesses, guides of routs and traffic informations, and auto navigation system with GPS(Global Positioning System).

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.73-82
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• 2014

The LM algorithm is used in solving the least square problem in a non linear system, and is used in various fields. However, in cases the applied field's target functionis complicated and high-dimensional, it takes a lot of time solving the inner matrix and vector operations. In such cases, the LM algorithm is unsuitable in embedded environment and requires a hardware accelerator. In this paper, we implemented the LM algorithm in hardware. In the implementation, we used pipeline stages to divide the target function operation, and reduced the period of data input of the matrix and vector operations in order to accelerate the speed. To measure the performance of the implemented hardware, we applied the refining fundamental matrix(RFM), which is a part of 3D reconstruction application. As a result, the implemented system showed similar performance compared to software, and the execution speed increased in a product of 74.3.

• Journal of the Korea Society of Computer and Information
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• v.10 no.3 s.35
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• pp.19-34
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• 2005

The difficulties in implementing of image processing algorithms are a major reason for the lack of research into algorithm comparison. This fact makes an image processing research with difficult. We conclude that it is important to represent algorithms in form of reusable code. Since current image processing systems do not fulfill all requirements we must pose on reusable implementations, we propose to solve the reuse problem by applying generic programming. We define two dimensional iterators, which mediate between image processing algorithms and their underlying data structures, so that the same algorithm implementation can be applied to any number of different image formats. The elegance and efficiency of this approach is illustrated by a number of useful examples and demonstrated by porting in existing image processing algorithm IDE(Integrated Development Environment).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.282-290
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• 2006

In this paper, we propose an enhanced Timing Estimator algorithm for 2.45GHz LR-WPAN receiver. Because an expensive and highly efficient oscillator can't be used for low-cost implementation, a Timing Estimator algorithm having stable operation in the channel environment with center frequency tolerance of 80 ppm is required. To enhance the robustness to frequency offset and the stability of receiver performance, multiple delay differential filter is adopted. By utilizing the characteristic that the correlation result between the output signal of Multiple delay differential filter and reference signal is restricted on the In-phase part of the correlator output, a coherent detection scheme instead of the typical noncoherent one is adopted for Timing Estimator. The application of the coherent detection scheme is suitable for LR-WPAN receiver aimed at low-cost, low-power, and low-complexity, since it can remove performance degradation due to squaring loss of I/Q squaring operation and decrease implementation complexity. Computer simulation results show that the proposed algorithm achieved performance improvement compared with the differential detection-based noncoherent scheme by 2dB in average.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.9
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• pp.2153-2160
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• 2015

An analysis of hardware design conditions of moving object detection (MOD) algorithm is described, which is based on effective Gaussian mixture learning (EGML). A simulation model of EGML algorithm is implemented using OpenCV, and the effects of some parameter values on background learning time and MOD sensitivity are analyzed for various images. In addition, optimal design conditions for hardware implementation of EGML-based MOD algorithm are extracted from fixed-point simulations for various bit-widths of parameters. The proposed fixed-point model of the EGML-based MOD uses only half of the bit-width at the expense of the loss of MOD performance within 0.5% when compared with floating-point MOD results.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.6
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• pp.955-961
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• 2017

In this paper, we propose a parallel approximate string matching algorithm with k-mismatches for multiple fixed-length patterns (PMASM) in DNA sequences. PMASM is developed from parallel single pattern approximate string matching algorithms to effectively calculate the Hamming distances for multiple patterns with a fixed-length. In the preprocessing phase of PMASM, all target patterns are binary encoded and stored into a look-up memory. With each input character from the input string, the Hamming distances between a substring and all patterns can be updated at the same time based on the binary encoding information in the look-up memory. Moreover, PMASM adopts graphics processing units (GPUs) to process the data computations in parallel. This paper presents three kinds of PMASM implementation methods in GPUs: thread PMASM, block-thread PMASM, and shared-mem PMASM methods. The shared-mem PMASM method gives an example to effectively make use of the GPU parallel capacity. Moreover, it also exploits special features of the CUDA (Compute Unified Device Architecture) memory structure to optimize the performance. In the experiments with DNA sequences, the proposed PMASM on GPU is 385, 77, and 64 times faster than the traditional naive algorithm, the shift-add algorithm and the single thread PMASM implementation on CPU. With the same NVIDIA GPU model, the performance of the proposed approach is enhanced up to 44% and 21%, compared with the naive, and the shift-add algorithms.