• Journal of information and communication convergence engineering
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• v.9 no.5
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• pp.602-606
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• 2011

It is necessary for developing specific application protocol for mobile sensor end nodes and data collection devices that have constrained resources and computing powers. Because of these needs, IETF WG developed CoAP protocol and Internet draft was released, and processing to international standardization of this protocol. Because sensor nodes and information collection devices have restricted resources and computing powers, there are some limitations for applying to this proposed protocol directly. Thus in this paper we shows the implementation of full CoAP protocol for server, works on Linux and CoAP-Lite over telos which works on TinyOS for information collection devices. In this implementation we verified the main activities of CoAP protocol over USN by modifying some hardware with dependent algorithm.

• Journal of computational fluids engineering
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• v.3 no.1
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• pp.22-29
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• 1998

Parallel implementation is conducted for a SIMPLER finite volume model. The present parallelism is based on domain decomposition and explicit message passing using MPI and SHMEM. Two parallel solvers to tridiagonal matrix equation are employed. The implementation is verified on the Cray T3E system for a benchmark problem of natural convection in a sidewall-heated cavity. The test results illustrate good scalability of the present parallel models. Performance issues are elaborated in view of convergence as well as conventional parallel overheads and single processor performance. The effectiveness of a localized matrix solution algorithm is demonstrated.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1556-1559
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• 1987

In this paper, a new state assignment method is proposed for the implementation of the area-effective control part. Introducing the, concept of adjacency matrix to control table generated by SDL(Symbolic Description Language) hardware compiler, a state assignment method is proposed with which minimal number of flip flops and effective number of product terms can be obtained to accomplish the area-effective implementation. Also, with substituting the assigned code to state transition table, boolean equations are obtained through 2-level logic minimization. Proposed algorithm is programmed in C-language on VAX-750/UNIX and b efficiency is shown by the practical example.

• Proceedings of the ESK Conference
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• 1997.04a
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• pp.196-199
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• 1997

This paper describes the implementation process of Virtual Modeling system for a customer-oriented product. The human sense is measured and analyzed by physical design factors and can be applied also for the product design. The first step implementing virtual modeling is to make a human sensibility("Kansei") database. Human sensibility database is constructed with the relational data of Kansei words and design factors. The next step is extraction the design information from the human sensibility database by fuzzy inference algorithm. This design information is used for the input data for the graphic database. Virtual implementation software compounds 3D shape of product. The final product can be modified according to the customer's requirement.quirement.

• Speech Sciences
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• v.8 no.2
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• pp.73-81
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• 2001

In this paper, we focus on the real time implementation of the single channel adaptive noise canceller(ANC) by using TMS320C30 EVM board. The implemented single channel adaptive noise canceller is based on a reference paper [1] in which it is simulated by using the recursive average magnitude difference function(AMDF) to get a properly delayed input speech on a sample basis as a reference signal and normalized least mean square(NLMS) algorithm. To certify results of the real time implementation, we measured the processing time of the ANC and enhancement ratio according to various signalto-noise ratios(SNRs). Experimental results demonstrate that the processing time of the speech signal of 32ms length with delay estimation of every 10 samples is about 26.3 ms, and almost the same performance as given in [1] is obtained with the implemented system.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.8
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• pp.18-25
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• 1992

Given a protocol specification, the task of testing whether an implementation conforms to the specification is called conformance testing. In this paper, the design and implementation of the protocol conformance test system using LAN on heterogeneous systems is descreibed. The test sequence used in this test system is generated using an algorithm on the basis of multiple UIO. The usability of this test system as an application was confirmed by performing the conformance test on the CCITT No.7 TCAP(transaction capabilities application part), implemented by ISDN Laboratory, Korea University in 1990.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.944-953
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• 1990

This paper describes design and implementation of a real-time high-precision vision system for an automation of SMT(surface mounting technology ). Also, a part inspection algorithm which calculates the position and direction of SMD(surface mounted device) accurately and performs the ruling using those information are presented, and a parallel processing technique for implementing those algorithms is also described. For a real-time implementation of iage acquisition and processing, several hardware modules, namely, multi-functional A/D-D/A board, frame memory board are developed. Particularly, a PE (processing element) board which employs the DSP56001 DSP (digital signal processor) is developed for the purpose of concurrent processing of part inspection algorithms. A stand-alone vision system is built by integration of the developed hardware modules and related softwares.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.1
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• pp.115-122
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• 2004

This paper describe the implementation or the boot loader for the boot system using of memory card. This boot roader consist of the system initialization, CF card checking, CF memory card checking, file system and the program relocator. This boot loader increase the system stability with program consistency checking algorithm in the read phase from the CF memory card. And this system have the compatibility in CF memory card file system, so system manufacturing productivity increase.

• Journal of Korea Society of Digital Industry and Information Management
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• v.13 no.3
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• pp.35-42
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• 2017

This paper presents hardware implementation of background timing-skew calibration technique for time-interleaved analog-to-digital converters (TI ADCs). The timing skew between any two adjacent analog-digital (A/D) channels is detected by using pure digital Finite Impulse Response (FIR) delay filter. This paper includes hardware architecture of the system, main units and small sub-blocks along with control logic circuits. Moreover, timing diagrams of logic simulations using ModelSim are provided and discussed for further understanding about simulations. Simulation process in MATLAB and Verilog is also included and provided with basic settings need to be done. For hardware implementation it not practical to work with all samples. Hence, the simulation is conducted on 512 TI ADC output samples which are stored in the buffer simultaneously and the correction arithmetic is done on those samples according to the time skew algorithm. Through the simulated results, we verified the implemented hardware is working well.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.14-16
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• 1988

With the development of VLSI technology, research on special processors for high-speed processing is on the increase and studies are focused on designing VLSI-oriented processors for signal processing. This paper processes a one-dimensional systolic array for Discrete Hartley Transform implementation and also processes processing element which is well described for algorithm. The discrete Hartley Transform(DHT) is a real-valued transform closely related to the DFT of a real-valued sequence can be exploited to reduce both the storage and the computation requried to produce the transform of real-valued sequence to a real-valued spectrum while preserving some of the useful properties of the DFT is something preferred. Finally, the architecture of one-dimensional 8-point systolic array, the detailed diagram of PE, total time units concept on implementation this arrays, and modularity are described.