• Title/Summary/Keyword: implementation algorithm

Search Result 4,233, Processing Time 0.036 seconds

Implementation of G.726 ADPCM Dual Rate Speech Codec of 16Kbps and 40Kbps (16Kbps와 40Kbps의 Dual Rate G.726 ADPCM 음성 codec구현)

  • Kim Jae-Oh;Han Kyong-Ho
    • Journal of IKEEE
    • /
    • v.2 no.2 s.3
    • /
    • pp.233-238
    • /
    • 1998
  • In this paper, the implementation of dual rate ADPCM using G.726 16Kbps and 40Kbps speech codec algorithm is handled. For small signals, the low rate 16Kbps coding algorithm shows almost the same SNR as the high rate 40Kbps coding algorithm , while the high rate 40Kbps coding algorithm shows the higher SNR than the low rate 16Kbps coding algorithm fur large signal. To obtain the good trade-off between the data rate and synthesized speech quality, we applied low rate 16Kbps for the small signal and high rate 40Kbps for the large signal. Various threshold values determining the rate are applied for good trade-off between data rate and speech quality. The simulation result shows the good speech quality at a low rate comparing with 16Kbps & 40Kbps.

  • PDF

ICS(Interference Cancellation System) in Wireless Repeater Using Complex Singed Singed LMS Algorithm (Complex Singed-Singed LMS 적응 알고리즘을 사용한 간섭제거 중계기(ICS)연구)

  • Lee, Seong-Jae;Park, Yong-Wan;Hong, Seung-Mo
    • Journal of the Institute of Electronics Engineers of Korea TC
    • /
    • v.48 no.10
    • /
    • pp.53-59
    • /
    • 2011
  • In recent years, mobile communication service is used extensively as a larger service area for the maintenance of quality of service required by the expansion of service areas and As the ever-increasing role in relays, and the location is relatively easy to install and less constrained costs, operating cost savings in terms of ICS(Interference Cancellation System) repeaters are required. However, an adaptive algorithm that is applied when updating the filter due to the increase in volume of operations increase the complexity of hardware implementation is fraught with many difficulties. In this paper, if there is a path that feedback. ICS repeater utilizing baseband signal processing for the removal of interfering signals from the feedback operation, significantly reducing the amount of reducing hardware complexity Complex Singed Signed LMS adaption algorithm is proposed. Proposed algorithm for evaluating the performance of Static channel WCDMA signal environment for the ICS, the results of the simulation algorithm, convergence speed and better performance in therms of convergence errors that are required through the implementation of the operation greatly reduces the amount of hardware complexity able to reduce the effect was visible.

Design and Implementation of Time Management Module for IEEE 1516 HLA/RTI (IEEE 1516 HLA/RTI 표준을 만족하는 시간 관리 서비스 모듈의 설계 및 구현)

  • Hong, Jeong-Hee;Ahn, Jung-Hyun;Kim, Tag-Gon
    • Journal of the Korea Society for Simulation
    • /
    • v.17 no.1
    • /
    • pp.43-52
    • /
    • 2008
  • The High Level Architecture(HLA) is the IEEE 1516 standard for interoperation between heterogeneous simulators which are developed with different languages and platforms. Run-Time Infrastructure(RTI) is a software which implements the HLA Interface Specification. With the development of time management service of RTI, it is necessary to consider an efficient design approach and an algorithm of Greatest Available Logical Time(GALT) computation. However, many time management services of existing RTIs have difficulty in modification and extension. Although some RTIs avoid this difficulty through modular design, they comply with not IEEE 1516 HLA/RTI but HLA 1.3. In addition, a lot of RTIs made use of well-known Mattern's algorithm for GALT computation. However, Mattern's algorithm has a few limitations for applying to IEEE 1516 HLA/RTI. This paper proposes a modular design and an implementation of time management service for IEEE 1516 HLA/RTI. We divided th time management service module into two sub-modules: a TIME module and a GALT module and used Mattern's algorithm improved for IEEE 1516 HLARTI. The paper also contains several experimental results in order to evaluate our time management service module.

  • PDF

Affine Projection Algorithm for Subband Adaptive Filters with Critical Decimation and Its Simple Implementation (임계 데시메이션을 갖는 부밴드 적응필터를 위한 인접 투사 알고리즘과 간단한 구현)

  • Choi, Hun;Bae, Hyeon-Deok
    • Journal of the Institute of Electronics Engineers of Korea SP
    • /
    • v.42 no.5 s.305
    • /
    • pp.145-156
    • /
    • 2005
  • In application for acoustic echo cancellation and adaptive equalization, input signal is highly correlated and the long length of adaptive filter is needed. Affine projection algorithms, in these applications, can produce a good convergence performance. However, they have a drawback that is a complex hardware implementation. In this paper, we propose a new subband affine projection algorithm with improved convergence and reduced computational complexity. In addition, we suggest a good approach to implement the proposed method. In this method by applying polyphase decomposition, noble identity and critical decimation to the anne projection algorithm the number of input vectors for decorrelation can be reduced. The weight-updating formula of the proposed method is derived as a simple form that compared with the NLMS(normalized least mean square) algorithm by the reduced projection order The efficiency of the proposed algorithm for a colored input signal was evaluated by using computer simulations.

Implementation of Quantum Gates for Binary Field Multiplication of Code based Post Quantum Cryptography (부호 기반 양자 내성 암호의 이진 필드 상에서 곱셈 연산 양자 게이트 구현)

  • Choi, Seung-Joo;Jang, Kyong-Bae;Kwon, Hyuk-Dong;Seo, Hwa-Jeong
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.24 no.8
    • /
    • pp.1044-1051
    • /
    • 2020
  • The age of quantum computers is coming soon. In order to prepare for the upcoming future, the National Institute of Standards and Technology has recruited candidates to set standards for post quantum cryptography to establish a future cryptography standard. The submitted ciphers are expected to be safe from quantum algorithm attacks, but it is necessary to verify that the submitted algorithm is safe from quantum attacks using quantum algorithm even when it is actually operated on a quantum computer. Therefore, in this paper, we investigate an efficient quantum gate implementation for binary field multiplication of code based post quantum cryptography to work on quantum computers. We implemented the binary field multiplication for two field polynomials presented by Classic McEliece and three field polynomials presented by ROLLO in generic algorithm and Karatsuba algorithm.

Efficient implementation of AES CTR Mode for a Mobile Environment (모바일 환경을 위한 AES CTR Mode의 효율적 구현)

  • Park, Jin-Hyung;Paik, Jung-Ha;Lee, Dong-Hoon
    • Journal of the Korea Institute of Information Security & Cryptology
    • /
    • v.21 no.5
    • /
    • pp.47-58
    • /
    • 2011
  • Recently, there are several technologies for protecting information in the lightweight device, One of them, the AES[1] algorithm and CRT mode, is used for numerous services(e,g, OMA DRM, VoIP, IPTV) as encryption technique for preserving confidentiality. Although it is possible that the AES algorithm CRT mode can parallel process transmitting data, IPTV Set-top Box or Mobile Device that uses these streaming service has limited computation-ability. So optimizing crypto algorithm and enhancing its efficiency for those environment have become an important issue. In this paper, we propose implementation method that can improve efficiency of the AES-CRT Mode by improving algorithm logics. Moreover, we prove the performance of our proposal on the mobile device which has limited capability.

An FPGA Implementation of Acoustic Echo Canceller Using S-LMS Algorithm (S-LMS 알고리즘을 이용한 음향반향제거기의 FPGA구현)

  • 이행우
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.41 no.9
    • /
    • pp.65-71
    • /
    • 2004
  • This paper describes a new adaptive algorithm which can reduce the required computation quantities in the adaptive filter. The proposed S-LMS algorithm uses only the signs of the normalized input signal rather than the input signals when coefficients of the filter are adapted. By doing so, there is no need for the multiplications and divisions which are mostly responsible for the computation quantities. To analyze the convergence characteristics of the proposed algorithm, the condition and speed of the convergence are derived mathematically. Also, we simulate an echo canceller adopting this algorithm and compare the performances of convergence for this algorithm with the ones for the other algorithm. As the results of simulations, it is proved that the echo canceller adopting this algorithm shows almost the same performances of convergence as the echo canceller adopting the SIA algorithm.

Fast 2-D Moving Target Tracking Algorithm (Fast 2차원 동 표적 추적 알고리즘)

  • Kim, Gyeong-Su;Lee, Sang-Uk;Song, Yu-Seop
    • Journal of the Korean Institute of Telematics and Electronics
    • /
    • v.22 no.1
    • /
    • pp.75-85
    • /
    • 1985
  • We have studied on the 2-D moving target tracking algorithm satisfying a real-time hardware implementation requirement. In this paper, a fast algorithm is developed based on the operator formulation and the variational algorithm f 10] . Here, we use the directed search for the maximum of the cross-correlation in order to obtain an initial estimate for the variational algorithm and decompose the scene into 16 smaller subblocks and apply the variational algorithm to each subblock sequentially with a new moving area detection method. We call the algorithm subblock based recursive algorithm. Compared with (10) , the ratio of the computational savings obtained from the proposed algorithm is 7 on the average.

  • PDF

Optimal sensor placement for health monitoring of high-rise structure based on collaborative-climb monkey algorithm

  • Yi, Ting-Hua;Zhou, Guang-Dong;Li, Hong-Nan;Zhang, Xu-Dong
    • Structural Engineering and Mechanics
    • /
    • v.54 no.2
    • /
    • pp.305-317
    • /
    • 2015
  • Optimal sensor placement (OSP) is an integral component in the design of an effective structural health monitoring (SHM) system. This paper describes the implementation of a novel collaborative-climb monkey algorithm (CMA), which combines the artificial fish swarm algorithm (AFSA) with the monkey algorithm (MA), as a strategy for the optimal placement of a predefined number of sensors. Different from the original MA, the dual-structure coding method is adopted for the representation of design variables. The collaborative-climb process that can make the full use of the monkeys' experiences to guide the movement is proposed and incorporated in the CMA to speed up the search efficiency of the algorithm. The effectiveness of the proposed algorithm is demonstrated by a numerical example with a high-rise structure. The results show that the proposed CMA algorithm can provide a robust design for sensor networks, which exhibits superior convergence characteristics when compared to the original MA using the dual-structure coding method.

Implementation of Anti-Collision Algorithm based on RFID System using FPGA (FPGA를 이용한 RFID 시스템 기반 충돌 방지 알고리즘 구현)

  • Lee, Woo-Gyeong;Kim, Sun-Hyung;Lim, Hae-Jin
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.10 no.3
    • /
    • pp.413-420
    • /
    • 2006
  • In this thesis, a RFID baseband system is implemented based on the international standard ISO/IEC 18000-6 Type-B using FPCA, and also anti-collision algorithm is implemented to improve the system performance. We compares the performance of the proposed anti-collision algorithm with that binary tree algorithm and bit-by-bit algorithm, and also validated analytic results using OPNET simulation. The proposed algorithm for Type-B transmission protocol and collision prohibition was designed using ISE7.1i which is a FPGA design-tool of Xilinx and implemented with Spartan2 chip which is a FPGA device.