• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.799-802
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• 2003

In this paper a FPGA implementation of WEP protocol is described. IEEE 802.11 specifies a wired LAN equivalent data confidentiality algorithm. WEP(Wired Equivalent Privacy) is defined as protecting authorized users of a wireless LAN from casual eavesdropping. WEP use RC4 algorithm for data encryption and decryption, also it use CRC-32 algorithm for error detection. The WEP protocol is implemented using Xilinx VirtexE XCV1000E-6HQ240C FPGA chip with PCI bus interface.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.171-174
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• 2000

This paper proposes a pipelined adaptive filter based on affine projection algorithm with order 2. This filter gives a better convergence performance than that of LMS or NLMS pipeline algorithm and has same latency with the pipeline algorithm based on equivalent transformation. Compared to the critical path of the pipeline NLMS implementation, only 2 additions are increased in that of the proposed implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.2
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• pp.259-267
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• 1997

The advent of B-ISDN using ATM(asynchronous transfer mode) made possible a variety of new multimedia services, however it also created a problem of congestion control due to bursty nature of various traffic sources. To tackle this problem, UPC/NPC(user parameter control/network parameter control) have been actively studied and DRLB(dynamic rate leaky bucket) algorithm, in which the token generation rate is changed according to states of data source andbuffer occupancy, is a good example of the UPC/NPC. However, the DRLB algorithm has drawbacks of low efficiency and difficult real-time implementation for bursty traffic sources because the determination of token generation rate in the algorithm is based on the present state of network. In this paper, we propose a more plastic and effective congestion control algorithm by combining the DRLB algorithm and neural network based prediction to remedy the drawbacks of the DRLB algorithm, and verify the efficacy of the proposed method by computer simulations.

• Journal of the Korea Society of Computer and Information
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• v.20 no.1
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• pp.1-10
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• 2015

In this paper, we propose an efficient parallel implementation method of a widely used complex four-stage fire detection algorithm using a graphics processing unit (GPU) to improve the performance of the algorithm and analyze the performance of the parallel implementation method. In addition, we use seven different resolution videos (QVGA, VGA, SVGA, XGA, SXGA+, UXGA, QXGA) as inputs of the four-stage fire detection algorithm. Moreover, we compare the performance of the GPU-based approach with that of the CPU implementation for each different resolution video. Experimental results using five different fire videos with seven different resolutions indicate that the execution time of the proposed GPU implementation outperforms that of the CPU implementation in terms of execution time and takes a 25.11ms per frame for the UXGA resolution video, satisfying real-time processing (30 frames per second, 30fps) of the fire detection algorithm.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.164-167
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• 2002

This paper presents the design of Rijndael crypto-processor with 128 bits, 192 bits and 256 bits key size. In October 2000 Rijndael cryptographic algorithm is selected as AES(Advanced Encryption Standard) by NIST(National Institute of Standards and Technology). Rijndael algorithm is strong in any known attacks. And it can be efficiently implemented in both hardware and software. We implement Rijndael algorithm in hardware, because hardware implementation gives more fast encryptioN/decryption speed and more physically secure. We implemented Rijndael algorithm for 128 bits, 192 bits and 256 bits key size with VHDL, synthesized with Synopsys, and simulated with ModelSim. This crypto-processor is implemented using on-the-fly key generation method and using lookup table for S-box/SI-box. And the order of Inverse Shift Row operation and Inverse Substitution operation is exchanged in decryption round operation of Rijndael algorithm. It brings about decrease of the total gate count. Crypto-processor implemented in these methods is applied to mobile systems and smart cards, because it has moderate gate count and high speed.

• ETRI Journal
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• v.22 no.3
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• pp.1-9
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• 2000

Self-Clocked Fair Queueing (SCFQ) algorithm has been considered as an attractive packet scheduling algorithm because of its implementation simplicity, but it has unbounded delay property in some input traffic conditions. In this paper, we propose a Rate Proportional SCFQ (RP-SCFQ) algorithm which is a rate proportional version of SCFQ. If any fair queueing algorithm can be categorized into the rate proportional class and input is constrained by a leaky bucket, its delay is bounded and the same as that of Weighted Fair Queueing (WFQ) which is known as an optimal fair queueing algorithm. RP-SCFQ calculates the timestamps of packets arriving during the transmission of a packet using the current value of system potential updated at every packet departing instant and uses a starting potential when it updates the system potential. By doing so, RP-SCFQ can have the rate proportional property. RP-SCFQ is appropriate for high-speed packet-switched networks since its implementation complexity is low while it guarantees the bounded delay even in the worst-case input traffic conditions.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.4
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• pp.166-171
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• 2006

In this paper, we have studied for analysis of the partial discharge(PD) signal in underground transmission line. The PD signal has estimated as detected signal accumulation of a PRPDA method by using Labview, and analyzed with fuzzy algorithm. In our algorithm, we developed system configuration that detected accumulating PD signal using by Labview and programmed fuzzy algorithm can be analyzed the PD signal using with Matlab. With practical PD logic implementation of theoretical detected system and hardware implementation, the device for Hipotronics Company's 50kV setup has generated and then has applied with $15k{\sim}17kV$ with 1:1 time probe. It's also used the LDPE 0.27mmt (scratch error 0.05mmt) to sample for making PD. In conclusion, Our new class of PD detected algorithm has also compared with previous PRPDA or Fuzzy algorithm. which has diagnose more conveniently by adding numerical values.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.2
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• pp.53-63
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• 2018

A novel real-time path planning algorithm suitable for implementation on a small mobile robot is introduced. The algorithm can be used as the basis for mapping unknown or partially known environments and is tested in a specially developed simulation environment in Matlab(R). Simulations results are presented demonstrating that the algorithm can readily be implemented to allow a small robot to navigate in various unknown and partially known environments. The main characteristics of the algorithm include simplicity, ease of implementation, speed, and efficiency, thereby being especially suitable for small robots. Furthermore, for partially known environments, another algorithm is proposed to predefine an optimal path taking into account information provided regarding the environment.

• Journal of the Korea Society of Computer and Information
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• v.7 no.3
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• pp.122-127
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• 2002

The Weighted Round Robin(na) discipline which is a sort of scheduling algorithm is quite simple and straightforward for handling multiple queues, and by Putting a different weight on each queue. In this paper, we propose new BSW structure, which can execute the WRR scheduling algorithm efficiently. Also, we develop a cell scheduling algorithm which is adapt in the new BSW structure. The Proposed BSW structure and the algorithm is capable of maintaining an allocated VC's weight correctly and decrease of average cell delay and maximum buffer length by serving other VC cell when empty in each VC queue. The proposed algorithm is a structure suitable for na implementation.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.560-563
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• 1999

In this paper, we present an optimal hardware implementation for preprocessing of a person identification algorithm utilizing vein pattern of dorsal surface of hand. For the vein pattern recognition, the computational burden of the algorithm lies mainly in the preprocessing of the input images, especially in lowpass filtering. we could reduce the identification time to one tenth by hardware design of the lowpass filter compared to sequential computations. In terms of the computation accuracy, the simulation results show that the CSD code provided an optimized coefficient value with about 91.62% accuracy in comparison with the floating point implementation of current coefficient value of the lowpass filter. The post-simulation of a VHDL model has been performed by using the ModelSim$^{TM}$. The implemented chip operates at 20MHz and has the operational speed of 55.107㎳.㎳.