• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.55 no.11
• /
• pp.502-510
• /
• 2006

In this paper, we describe implementation of a computer access device for the severly motor-disability. Many people with severe motor disabilities need an augmentative communication technology. Those who are totally paralyzed, or 'locked-in' cannot use conventional augmentative technologies, all of which require some measure of muscle control. The forehead is often the last site to suffer degradation in cases of severe disability and degenerative disease. For example, In ALS(Amyotrophic Lateral Sclerosis) and MD(Muscular dystrophy) the ocular motorneurons and ocular muscles are usually spared permitting at least gross eye movements, but not precise eye pointing. We use brain and body forehead bio-potentials in a novel way to generate multiple signals for computer control inputs. A bio-amplifier within this device separates the forehead signal into three frequency channels. The lowest channel is responsive to bio-potentials resulting from an eye motion, and second channel is the band pass derived between 0.5 and 45Hz, falling within the accepted Electroencephalographic(EEG) range. A digital processing station subdivides this region into eleven components frequency bands using FFT algorithm. The third channel is defined as an Electromyographic(EMG) signal. It responds to contractions of facial muscles and is well suited to discrete on/off switch closures, keyboard commands. These signals are transmitted to a PC that analyzes in a time series and a frequency region and discriminates user's intentions. That software graphically displays user's bio-potential signals in the real time, therefore user can see their own bio-potentials and control their physiological signals little by little after some training sessions. As a result, we confirmed the performance and availability of the developed system with experimental user's bio-potentials.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.24 no.5
• /
• pp.987-999
• /
• 2014

A PUF is embedded and implemented into a tag or a device, and outputs a noise y with an input of x, based on its own unique physical characteristics. Although x is used multiple times as inputs of PUF, the PUF outputs slightly different noises, ($y_1,{\cdots}y_n$), and also the PUF has tamper-resistance property, hence it has been widely used in cryptographic protocol. In this paper, we study how to design a PUF-based RFID authentication protocol in a secure and an efficient way. Compared with recent schemes, the proposed scheme guarantees both authentication and privacy of backword/forward under the compromise of long-term secrets stored in tag. And also, the most cost and time-consumming procedure, key recovery algorithm used with PUF, has been desgined in the side of RFID reader, not in the tag, and, consequently, gives possibility to minimize costs for implementation and running time.

• Journal of Navigation and Port Research
• /
• v.39 no.4
• /
• pp.307-312
• /
• 2015

ARPA(Automatic Radar Plotting Aid) is a device to calculate CPA(closest point of approach)/TCPA(time of CPA), true course and speed of targets by vector operation of relative courses and speeds. The purpose of this study is to develop target acquisition and tracking technology for ARPA Radar implementation. After examining the previous studies, applicable algorithms and technologies were developed to be combined and basic ARPA functions were developed as a result. As for main research contents, the sequential image processing technology such as combination of grayscale conversion, gaussian smoothing, binary image conversion and labeling was deviced to achieve a proper target acquisition, and the NNS(Nearest Neighbor Search) algorithm was appllied to identify which target came from the previous image and finally Kalman Filter was used to calculate true course and speed of targets as an analysis of target behavior. Also all technologies stated above were implemented as a SW program and installed onboard, and verified the basic ARPA functions to be operable in practical use through onboard test.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.9
• /
• pp.2229-2236
• /
• 2014

In this paper, we proposed and implemented the automated cable-spreading program which can be done effectively cabling plan for electrical equipment in power plant. Cause the process of existing cable-spreading design was written in by hand, there are grossly inefficient gain by a personal and time investment with cable omission and unfixed overfill value. Proposed automation program for cable-spreading, which is coded cable and raceway, can calculate the overfill value and raceway change. Some experiments are conducted so as to verify the proposed model, and as a result, implemented cable-spreading program is well performed.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.3
• /
• pp.643-650
• /
• 2014

A hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is described. The designed phase calculator adopts redundant binary number systems and a pipelined architecture to improve throughput and speed. It performs arctangent operation using vectoring mode of DCORDIC(Differential COordinate Rotation DIgital Computer) algorithm. Fixed-point MATLAB simulations are carried out to determine the optimal bit-widths and number of iteration. The phase calculator has ben verified by FPGA-in-the-loop verification using MATLAB/Simulink. A test chip has been fabricated using a TSMC $0.18-{\mu}m$ CMOS process, and test results show that the chip functions correctly. It has 82,000 gates and the estimated throughput is 400 MS/s at 400Mhz@1.8V.

• Journal of KIISE:Software and Applications
• /
• v.31 no.4
• /
• pp.498-504
• /
• 2004

This paper presents a new text classifier based on a feature projection technique. In feature projections, training documents are represented as the projections on each feature. A classification process is based on individual feature projections. The final classification is determined by the sum from the individual classification of each feature. In our experiments, the proposed classifier showed high performance. Especially, it have fast execution speed and robustness with noisy data in comparison with k-NN and SVM, which are among the state-of-art text classifiers. Since the algorithm of the proposed classifier is very simple, its implementation and training process can be done very simply. Therefore, it can be a useful classifier in text classification tasks which need fast execution speed, robustness, and high performance.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.11C
• /
• pp.1541-1550
• /
• 2004

In this paper, we propose an advanced hardware architecture for fast multi-resolution motion estimation of the video coding standard MPEG-1,2 and MPEG-4 AVC. We describe the algorithm and derive hardware architecture emphasizing the importance of area for low cost and fast operation by using the shared memory, the special ram architecture, the motion vector for 4 pixel x 4 pixel, the spiral search and so on. The proposed architecture has been verified by ARM-interfaced emulation board using Excalibur Altera FPGA and also by ASIC synthesis using Samsung 0.18 m CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 140 MHz, processing more than 1,100 QCIF video frames or 70 4CIF video frames per second. The hardware is going to be used as a core module when implementing a complete MPEG-4 AVC video encoder ASIC for real-time multimedia application.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.38A no.9
• /
• pp.798-809
• /
• 2013

In this paper, we propose robust relay and destination filter design methods for the multi-user peer-to-peer amplify-and-forward relaying systems while taking imperfect channel knowledge into consideration. Specifically, the relay and destination filter sets are developed to minimize the sum mean-squared-error (MSE). We first present a robust joint optimum relay and destination filter calculation method with an iterative algorithm. Motivated by the need to reduce computational complexity of the iterative scheme, we then formulate a simplified sum MSE minimization problem using the relay filter decomposability, which lead to two robust sub-optimum non-iterative design methods. Finally, we propose robust modified destination filter design methods which require only local channel state information between relay node and a specific destination node. The analysis and simulation results verify that, compared with the optimum iterative method, the proposed non-iterative schemes suffer a marginal loss in performance while enjoying significantly improved implementation efficiencies. Also it is confirmed that the proposed robust filter design methods provide desired robustness in the presence of channel uncertainty.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.7 no.1
• /
• pp.81-90
• /
• 2002

This paper presents an Implementation of digital high-performance position sensorless control system of Reluctance Synchronous Motor(RSM) drives with Direct Torque Control(DTC). The system consists of stator flux observer, speed and torque estimator, two digital hysteresis controllers, an optimal switching look-up table, Insulated Gate Bipolar Transistor(IGBT) voltage source inverter, and TMS320C31 DSP board. The stator flux observer Is based on the combined voltage and current model with stator flux feedback adaptive control of which inputs are current and voltage sensed on motor terminal for wide speed range. In order to prove the suggested sensorless control algorithm for industrial field application, we have some simulation and actual experiment at low and high speed range. The developed high-performance speed control by fully digital system are shown a good response characteristic of control results and high performance features using 1.0[kW] RSM having 2.57 reluctance ratio of $L_d/L_q$.

• The KIPS Transactions:PartC
• /
• v.9C no.1
• /
• pp.65-72
• /
• 2002

In this paper, we implement a high-speed swatch tilth the function for label integration to enhance the expansion of networks using the label space of routers efficiently on MPLS over ATM networks. We propose an appropriate hardware structure to support the VC-merge function and differentiated services simultaneously. In this paper, we use the adaptive congestion control method such as EPD algorithm in carte that there is a possibility of network congestion in output buffers of each core LSR. In addition, we justify the validity of the proposed VC-merge method through simulation and comparison to conventional Non VC-merge methods. The proposed VC-merge capable switch is modeled in VHDL. synthesized, and fabricated using the SAMSUNG 0.5um SOG process.