• The Journal of the Acoustical Society of Korea
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• v.15 no.1E
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• pp.89-94
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• 1996

This paper deals with the application of the LMS algorithm as a decision-directed adaptive equalizer in a communication receiver which also employs a sophisticated decoding scheme such as the Viterbi algorithm, in which the desired signal, hence the error, is not available until several symbol intervals later because of decoding delay. In such applications the implemented weight updating algorithm becomes DLMS and major penalty is reduced convergence speed. Therefore, every effort should by made to keep the delay as small as possible if it is not avoidable. In this paper we present a modified implementation in which the effects of the decoding delay can be avioded and perform some computer simulations to check the validity and the performance of the new implementation.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.1379-1382
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• 1997

We introduce a fast implementation of the adaptive transversal filter which uses least-mean-square(LMS) algorithm. The fast Hadamard transform(FHT) is used for the implementation of the filter. By using the proposed filter we can get the significant time reduction in computatioin over the conventional time domain LMS filter at the cost of a little performance. By computer simulation, we show the comparison of the propsed Hadamard-domain filter and the time domain filter in the view of multiplication time, mean-square error and robustness for noise.

• Proceedings of the Optical Society of Korea Conference
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• 1991.06a
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• pp.35-40
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• 1991

In this paper, a new adaptive learning algorithm, Training by Adaptive Gain (TAG) for optical implementation of large-sized neural networks has been developed and its electro-optical implementation for 2-dimensional input and output neurons has been demostrated. The 4-dimensional global fixed interconnections and 2-dimensional adaptive gain-controls are implemented by multi-facet computer generated holograms and LCTV spatial light modulators, respectively. When the input signals pass through optical system to the output classifying layer, the TAG adaptive learning algorithm is implemented by a personal computer. The system classifies three 5$\times$5 input patterns correctly.

• Journal of Korea Society of Digital Industry and Information Management
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• v.17 no.2
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• pp.13-20
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• 2021

Placement is a very important step in the VLSI physical design process. It is the problem of placing circuit modules to optimize the circuit performance and reliability of the circuit. It is used at the layout level to find strongly connected components that can be placed together in order to minimize the layout area and propagation delay. The most popular algorithms for circuit placement include the cluster growth, simulated annealing, integer linear programming and genetic algorithm. In this paper we propose a adapted genetic algorithm searching solution space for the placement problem, and then compare it with simulated annealing and genetic algorithm by analyzing the results of each implementation. As a result, it was found that the adaptive genetic algorithm approaches the optimal solution more effectively than the simulated annealing and genetic algorithm.

• Korean Management Science Review
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• v.15 no.1
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• pp.1-12
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• 1998

This paper discusses a new algorithm, the PAPANET (Pivot And Probe Algorithm for NETwork optimization), for solving linear, capacitated linear network flow problem (NPs), PAPANET is a variation and specialization of the Pivot And Probe Algorithm (PAPA) developed by Sethi and Thompson, published in 1983-1984. PAPANET first solves an initial relaxed NP (RNP) with all the nodes from the original problem and a limited set of arcs (possibly all the artificial and slack arcs). From the arcs not considered in the current relaxation, we PROBE to identify candidate arcs that violate the current solution's dual constraints maximally. Candidate arcs are added to the RNP, and this new RNP is solved to optimality. This candidate pricing procedure and pivoting continue until all the candidate arcs price unfavorably and all of the dual constraints corresponding to the other, so-called noncandidate arcs, are satisfied. The implementation of PAPANET requires significantly fewer arcs and less solution CPU time than is required by the standard network simplex method implementation upon which it is based. Computational tests on randomly generated NPs indicate that our PAPANET implementation requires up to 40-50% fewer pivots and 30-40% less solution CPU time than is required by the comparable standard network simplex implementation from which it is derived.

• Journal of Korea Multimedia Society
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• v.4 no.1
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• pp.82-90
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• 2001

Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. This paper proposes a new type of embedded one chip computer fort Hardware Implementation of Genetic Algorithm. The proposed embedded one chip computer consists of 16 Bit CPU care and hardware of genetic algorithm. In contrast to conventional hardware oriented GA which is dependent on main computer in the process of GA, the proposed embedded one chip computer is independent on main computer. Conventional hardware GA uses the fixed length of chromosome but the proposed embedded one chip computer uses the variable length of chromosome by employing the efficient 16 bit Pipeline Unit. Experimental results show that the proposed one chip computer is applicable to the design of evolvable hardware for Random NRZ bit synchronization circuit.

• Proceedings of the IEEK Conference
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• 2000.06d
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• pp.178-181
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• 2000

In this paper, we present the implementation of filterbank for MPEG-2 Advanced Audio Coding (AAC) decoder with VHDL. The filterbank of AAC employs a technique called time-domain aliasing cancellation (TDAC). In order to make the algorithm more efficiently, we decompose and reorganize the filterbank algorithm lot the high speed decoding process and lower computational cost. And we make this filterbank algorithm to be used with other modules of AAC decoder in parallel processing.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.1
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• pp.107-114
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• 1994

Hardware implementation of the on-chip learning artificial neural networks is important for real-time processing. A pRAM model is based on probabilistic firing of a biological neuron and can be implemented in the VLSI circuit with learning capability. We derive a backpropagation learning algorithm for the pRAM networks and present its circuit implementation with stochastic computation. The simulation results confirm the good convergence of the learning algorithm for the pRAM networks.

• Journal of information and communication convergence engineering
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• v.8 no.5
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• pp.493-497
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• 2010

This paper address the problem of tracking multiple objects encountered in many situation in developing condensation algorithms. The difficulty lies on the fact that the implementation of condensation algorithm is not easy for the general users. We propose an automatic code generation program for condensation algorithm using MATLAB tool. It will help for general user who is not familiar with condensation algorithm to apply easily for real system. The merit of this program is that a general industrial engineer can easily simulate the designed system and confirm the its performance on the fly.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.131.1-131
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• 2001

At the present time, multimedia chip, internet application, and network equipment is designed by using ARM core. Because it has a good debugging, software compiler and needed low power. We must process a data coding to send a multimedia data by real time. So need to connect software and hardware algorithm. In this research, We design interface for ARM9/AMBA based board using VHDL for these function implementation. The board is used the ARM company´s ARM940T for software function implementation and Xilinx company´s Virtex E2000 for hardware function algorithm. The various hardware algorithm (ME,ME,DCT) block for performance can be implemented on this system.