• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.11
• /
• pp.8-15
• /
• 2009

Side-channel attacks including the differential power analysis attack are often more powerful than classical cryptanalysis and have to be seriously considered by cryptographic algorithm's implementers. Various countermeasures have been proposed against such attacks. In this paper, we deal with the masking method, which is known to be a very effective countermeasure against the differential power analysis attack and propose new gate-level conversion methods between Boolean and arithmetic masks. The new methods require only 6n-5 XOR and 2n-2 AND gates with 3n-2 gate delay for converting n-bit masks. The basic idea of the proposed methods is that the carry and the sum bits in the ripple adder are manipulated in a way that the adversary cannot detect the relation between these bits and the original raw data. Since the proposed methods use only bitwise operations, they are especially useful for DPA-securely implementing cryptographic algorithms in hardware which use both Boolean and arithmetic operations. For example, we applied them to securely implement the block encryption algorithm SEED in hardware and present its detailed implementation result.

• Journal of IKEEE
• /
• v.22 no.2
• /
• pp.495-498
• /
• 2018

In this paper, we propose an DAP system for dose evaluation of medical and industrial X-ray generator. Based on the DAP measurement technique using the Ion-Chamber, the proposed system can clearly measure the exposure radiation dose generated by the diagnostic X-ray apparatus. The hardware part of the DAP measures the amount of charge in the air that is captured by an X-ray. The high-speed processing algorithm part for cumulative radiation dose measurement through microcurrent measures the amount of charge captured by X-ray at a low implementation cost (power) with no input loss. The wired/wireless transmission/reception protocol part synchronized with the operation of the X-ray generator improves communication speed. The PC-based control program part for interlocking and aging measures the amount of X-ray generated in real time and enables measurement graphs and numerical value monitoring through PC GUI. As a result of evaluating the performance of the proposed system in an accredited testing laboratory, the measured values using DAP increased linearly in each energy band (30, 60, 100, 150 kV). In addition, since the standard deviation of the measured value at the point of 4 division was ${\pm}1.25%$, it was confirmed that the DAP showed uniform measurements regardless of location. It was confirmed that the normal operation was not less than ${\pm}4.2%$ of the international standard.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.4
• /
• pp.41-49
• /
• 2010

This paper proposes a new high speed SHA-1 architecture using multiple unfolding and pre-computation techniques. We unfolds iterative hash operations to 2 continuos hash stage and reschedules computation timing. Then, the part of critical path is computed at the previous hash operation round and the rest is performed in the present round. These techniques reduce 3 additions to 2 additions on the critical path. It makes the maximum clock frequency of 118 MHz which provides throughput rate of 5.9 Gbps. The proposed architecture shows 26% higher throughput with a 32% smaller hardware size compared to other counterparts. This paper also introduces a analytical model of multiple SHA-1 architecture at the system level that maps a large input data on SHA-1 block in parallel. The model gives us the required number of SHA-1 blocks for a large multimedia data processing that it helps to make decision hardware configuration. The hs fospeed SHA-1 is useful to generate a condensed message and may strengthen the security of mobile communication and internet service.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.44 no.5
• /
• pp.62-70
• /
• 2007

In this paper, the boost Power Factor Correction(PFC) technique for Direct Torque Control(DTC) of brushless DC motor drive in the constant torque region is implemented on a TMS320F2812DSP. Unlike conventional six-step PWM current control, by properly selecting the inverter voltage space vectors of the two-phase conduction mode from a simple look-up table at a predefined sampling time, the desired quasi-square wave current is obtained, therefore a much faster torque response is achieved compared to conventional current control. Furthermore, to eliminate the low-frequency torque oscillations caused by the non-ideal trapezoidal shape of the actual back-EMF waveform of the BLDC motor, a pre-stored back-EMF versus position look-up table is designed. The duty cycle of the boost converter is determined by a control algorithm based on the input voltage, output voltage which is the dc-link of the BLDC motor drive, and inductor current using average current control method with input voltage feed-forward compensation during each sampling period of the drive system. With the emergence of high-speed digital signal processors(DSPs), both PFC and simple DTC algorithms can be executed during a single sampling period of the BLDC motor drive. In the proposed method, since no PWM algorithm is required for DTC or BLDC motor drive, only one PWM output for the boost converter with 80 kHz switching frequency is used in a TMS320F2812 DSP. The validity and effectiveness of the proposed DTC of BLDC motor drive scheme with PFC are verified through the experimental results. The test results verify that the proposed PFC for DTC of BLDC motor drive improves power factor considerably from 0.77 to as close as 0.9997 with and without load conditions.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.38 no.1
• /
• pp.27-34
• /
• 2001

The multiplication algorithm using the primitive irreducible trinomial $x^m+x+1$ over $GF(2^m)$ was proposed by Mastrovito. The multiplier proposed in this paper consisted of the multiplicative operation unit, the primitive irreducible operation unit and mod operation unit. Among three units mentioned above, the Primitive irreducible operation was modified to primitive irreducible trinomial $x^m+x+1$ that satisfies the range of 1$x^m,{\cdots},x^{2m-2}\;to\;x^{m-1},{\cdots},x^0$ is reduced. In this paper, the primitive irreducible polynomial was reduced to the primitive irreducible trinomial proposed. As a result of this reduction, the primitive irreducible trinomial reduced the size of circuit. In addition, the proposed design of multiplier was suitable for VLSI implementation because the circuit became regular and modular in structure, and required simple control signal.

• Journal of Korea Multimedia Society
• /
• v.7 no.11
• /
• pp.1597-1609
• /
• 2004

A lot of lipreading system has been proposed to compensate the rate of speech recognition dropped in a noisy environment. Previous lipreading systems work on some specific conditions such as artificial lighting and predefined background color. In this paper, we propose a real-time lipreading system which allows the motion of a speaker and relaxes the restriction on the condition for color and lighting. The proposed system extracts face and lip region from input video sequence captured with a common PC camera and essential visual information in real-time. It recognizes utterance words by using the visual information in real-time. It uses the hue histogram model to extract face and lip region. It uses mean shift algorithm to track the face of a moving speaker. It uses PCA(Principal Component Analysis) to extract the visual information for learning and testing. Also, it uses HMM(Hidden Markov Model) as a recognition algorithm. The experimental results show that our system could get the recognition rate of 90% in case of speaker dependent lipreading and increase the rate of speech recognition up to 40～85% according to the noise level when it is combined with audio speech recognition.

• The Journal of the Acoustical Society of Korea
• /
• v.15 no.2
• /
• pp.21-32
• /
• 1996

The performance of the energy density control algorithm for controlling a broadband noise is evaluated in a one-dimensional enclosure. To avoid noncausality problem of a control filter, which often happens in a frequency domain optimization, analyses presented in this paper are undertaken in the time domain. This approach provides the form of the causally constrained optimal controller. Numerical results are presented to predict the performance of the active noise control system, and indicate that imp개ved global attenuation of the broadband noise can be achieved by minimizing the energy density, rather than the squared pressure. It is shown that minimizing the energy density at a single location yields global attenuation results that are comparable to minimizing the potential energy. Furthermore, unlike the squared pressure control, the energy density control does not demonstrate any dependence on the error sensor location for this one-dimensional field. A practical implementation of the energy-based control algorithm is presented. Results show that the energy density control can be implemented using the two sensor technique with a tolerable margin of performance degradation.

• The KIPS Transactions:PartD
• /
• v.10D no.1
• /
• pp.1-12
• /
• 2003

Recently, there have been many indexing schemes for multimedia data such as image, video data. But recent database applications, for example data mining and multimedia database, are required to support multi-user environment. In order for indexing schemes to be useful in multi-user environment, a concurrency control algorithm is required to handle it. So we propose a concurrency control algorithm that can be applied to CBF (cell-based filtering method), which uses the signature of the cell for alleviating the dimensional curse problem. In addition, we extend the SHORE storage system of Wisconsin university in order to handle high-dimensional data. This extended SHORE storage system provides conventional storage manager functions, guarantees the integrity of high-dimensional data and is flexible to the large scale of feature vectors for preventing the usage of large main memory. Finally, we implement the web-based image retrieval system by using the extended SHORE storage system. The key feature of this system is platform-independent access to the high-dimensional data as well as functionality of efficient content-based queries. Lastly. We evaluate an average response time of point query, range query and k-nearest query in terms of the number of threads.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.3C
• /
• pp.398-407
• /
• 2004

In this paper, a blind watermarking method which is suitable to the video compression using 2-D discrete wavelet transform was proposed and implemented into the hardware using VHDL(VHSIC Hardware Description Language). The goal of the proposed watermarking algorithm is the authentication about the manipulation of the watermark embedded image and the detection of the error positions. Considering the compressed video image, the proposed watermarking scheme is unrelated to the quantization and is able to concurrently embed or extract the watermark. We experimentally verified that the lowest frequency subband(LL4) is not sensitive to the change in the spatial domain, so LL4 subband was selected for the mark space. And the combination of the bitplanes which has the properties of both the minimum degradation of the image and the robustness was chosen as the embedded Point in the mark space in LL4 subband. Since we know the watermark embedded positions and the watermark is embedded by not varying the value but changing the value, the watermark can be extracted without the original image. Also, for the security when exposing the watermark embedded position, we embed the encrypted watermark by the block cipher. The proposed watermark algorithm shows the robustness against the general image manipulation and is easily transplanted into the image or video compressor with the minimal changing in the structure. The designed hardware has 4037 LABs(24％) and 85 ESBs(3％) in APEX20KC EP20K400CF672C7 FPGA of Altera and stably operates in 82MHz clock frequency.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.11 no.5
• /
• pp.1564-1572
• /
• 2010

In this study, the falls detection and direction classification system was implemented using 3-axial acceleration signal. The acceleration signals were acquired from the 3-axial accelerometer(MMA7260Q, Freescale, USA), and then transmitted to the computer through USB interface. The implemented system can detect falls using the newly proposed algorithm, and also classify the direction of falls using fuzzy classifier. The 6 subjects was selected for experiment and the accelerometer was attached on each subject's chest. Each subject walked in normal pace for 5 seconds, and then the fall down according to the four direction(front_fall, back_fall, left_fall and right_fall) during at least 2 second. The falls was easily detect using the newly proposed algorithm in this study. The acquired signals were analyzed after 1 second from generating falls. The fuzzy classifier was used to classify the direction of falls. The mean value of the falls detection rate was 94.79%. The classifier rate according to falls direction were 95.83% in case of front falls, 100% incase of back falls, 87.5% in case of left falls, and 95.83% in case of right falls.