• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.1
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• pp.96-102
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• 1995

This paper presents the VHSIC Hardware Description Language(VHDL) implementation of the Fixed Point Covariance Lattice(FLAT) algorithm for an Linear Predictive Coding(LPC) analysis and its related algorithms, such as the forth order high pass Infinite Impulse Response(IIR) filter, covariance matrix calculation, and Spectral Smoothing Technique(SST) in the Vector Sum Exited Linear Predictive(VSELP) speech coder that has been Selected as the standard speech coder for the North America and Japanese digital cellular. Existing Digital Signal Processor(DSP) chips used in digital cellular phones are derived from general purpose DSP chips, and thus, these DSP chips may not be optimal and effective architectures are to be designed for the above mentioned algorithms. Then we implemented the VHDL code based on the C code, Finally, we verified that VHDL results are the same as C code results for real speech data. The implemented VHDL code can be used for performing logic synthesis and for designing an LPC Application Specific Integrated Circuit(ASOC) chip and DsP chips. We first developed the C language code to investigate the correctness of algorithms and to compare C code results with VHDL code results block by block.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.24-33
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• 2012

This paper describes a multi-mode LDPC decoder which supports 19 block lengths and 6 code rates of Quasi-Cyclic LDPC code for Mobile WiMAX system. To achieve an efficient implementation of 114 operation modes, some design optimizations are considered including block-serial layered decoding scheme, a memory reduction technique based on the min-sum decoding algorithm and a novel method for generating the cyclic shift values of parity check matrix. From fixed-point simulations, decoding performance and optimal hardware parameters are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 380,000 gates and 52,992 bits RAM, and the estimated throughput is about 164 ~ 222 Mbps at 56 MHz@1.8 V.

• International Journal of Ocean System Engineering
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• v.1 no.2
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• pp.102-109
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• 2011

This paper describes the implementation of a precise underwater navigation solution using a multiple sensor fusion technique based on USBL, GPS, DVL and AHRS measurements for the operation of a remotely operated mine disposal vehicle (MDV). The estimation of accurate 6DOF positions and attitudes is the key factor in executing dangerous and complicated missions. To implement the precise underwater navigation, two strategies are chosen in this paper. Firstly, the sensor frame alignment to the body frame is conducted to enhance the performance of a standalone dead-reckoning algorithm. Secondly, absolute position data measured by USBL is fused to prevent cumulative integration error. The heading alignment error is identified by comparing the measured absolute positions with the DR algorithm results. The performance of the developed approach is evaluated with the experimental data acquired by MDV in the South-sea trial.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5C
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• pp.692-699
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• 2004

In this paper we studied an implementation of QR decomposition-based RLS algorithm using modified Givens rotation method. Givens rotation can be obtained with a sequence of the CORDIC operations. In order to reduce the computing time of QR decomposition we restricted the number of iterations of the CORDIC operation per a Givens rotation and used double-rotation method to remove the square-root in the scaling factor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.4C
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• pp.379-388
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• 2007

In this paper, we propose an adaptive turbo decoding algorithm for high order modulation scheme combined with originally design for a standard rate-1/2 turbo decoder for B/QPSK modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/QPSK turbo decoder without any modifications. Adaptive turbo decoder process the received symbols recursively to improve the performance. As the number of iterations increase, the execution time and power consumption also increase as well. The source of the latency and power consumption reduction is from the combination of the radix-4, dual-path processing, parallel decoding, and early-stop algorithms. We implemented the proposed scheme on a field-programmable gate array (FPGA) and compared its decoding speed with that of a conventional decoder. From the result of implementation, we confirm that the decoding speed of proposed adaptive decoding is faster than conventional scheme by 6.4 times.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.334-336
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• 2005

According as quality of life improves, pursuit of agreeable iife became realistic problem. Specially, noise had been appraised to element that infiuence in human life directly and indirectly Therefore, necessity of study about noise control is increased for better labor conditions and agreeable habitat. In this paper, implementation of active mufflers using recursive LMS algorithms is presented. Analyze exhaust pipe noise of a gasoline and Diesel car and use adaptation IIR filter algorithm that stability is solidified and controled exhaust pipe noise of a car. computer simulation is performed to show the effectiveness of a proposed algorithm.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.641-642
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• 2008

In this paper, we propose a new approach for the implicit rating algorithm of finding user's intense and preference to the contents on the web. Although the explicit method dig out the user preference of specific contents based on the user's intervention, we propose the implicit method obtaining the user preference according to the user's behavioral patterns on the web implicitly and automatically without the user's intervention. The implementation results show that the proposed approach is highly valuable for supporting recommender systems in conjunction with the users lifestyle.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1284-1287
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• 2002

A fast algorithm for a circular pattern recognition from a binary edge image is proposed in this paper. The implementation of this algorithm onto an FPGA is designed using Verilog-HDL where a target device is Altera EPF10K100ARC240-3. For a 256 ${\times}$ 256-pixe1 binary edge image assuming a real watermelon in a greenhouse, improved circuit performance of the proposed design was confirmed.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.41-44
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• 1999

In this paper we proposed the algorithm for the implementation of network interface unit transmitter and analyzed its performance in broadband wireless local loop. The symbol rate of upstream transmitter is variable since the channel bandwidth of upstream can vary. Assuming that master clock ( $f_{DAC}$) is fixed, the cubic interpolator of Farrow structure is used to increase the sample rate to master clock rate. Simulation shows that the signal to noise ratio is about 54~55 dB and spurious signal power of upstream transmitter is less than 45 dB.B.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.9
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• pp.76-84
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• 1994

This paper presents a new high-performance VLSI architecture and VLSI implementation for full-search block matching algorithm. The proposed VLSI architecture has the feature of two directional parallel and pipeline processing, thereby reducing the PE idle time at which the direction of block matching operation within the search area is changed. Therfore, the proposed architecture is faster than the existing architectures under the same clock frequency. Based on HSPICE circuit simulation, it is verified that the implemented procesing element is operated successfully within 13 ns for 75 MHz operation.